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CRC32 Discrepancy

Dear 4DSP,

I have gone through the verilog code of CRC32 designed by you but I am not able to find any standard CRC 32 calculator results matching with the simulations results from the code of module crc_32 given by you. We are using FMC 112 hardware with ML605. On the other hand following code shown below which I have got generated from opencores.org gives common results with standard CRC 32 calculator given on net. We have checked that equations are also different. It is not that we have not checked initial settings etc. but still I am not able to get the scheme developed by 4DSP for CRC32 computation.

We are using this case of the code given by you:-

  else if (calc & d_valid) begin
      crc_reg <= next_crc;
      crc    <= ~{next_crc[24], next_crc[25], next_crc[26], next_crc[27],
                  next_crc[28], next_crc[29], next_crc[30], next_crc[31]};
  end

We request you to kindly show more light on it. Below is standard VHDL code where results match with standard given in this link https://ghsi.de/CRC/index.php?Polynom=100000100110000010001110110110111&Message=01 if i make initial condition all '0'.

Seeking your help in understanding...


----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    15:05:14 02/17/2015
-- Design Name:
-- Module Name:    crc_gen_32 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

-- CRC module for data(7:0)
--  lfsr(31:0)=1+x^1+x^2+x^4+x^5+x^7+x^8+x^10+x^11+x^12+x^16+x^22+x^23+x^26+x^32;
-------------------------------------------------------------------------------

entity crc_gen_32 is
  port ( data_in : in std_logic_vector (7 downto 0);
    crc_en , rst, clk : in std_logic;
    crc_out : out std_logic_vector (31 downto 0));
end crc_gen_32;

architecture Behavioral of crc_gen_32 is
  signal lfsr_q: std_logic_vector (31 downto 0);
  signal lfsr_c: std_logic_vector (31 downto 0);
begin
    crc_out <= lfsr_q;

    lfsr_c(0) <= lfsr_q(24) xor lfsr_q(30) xor data_in(0) xor data_in(6);
    lfsr_c(1) <= lfsr_q(24) xor lfsr_q(25) xor lfsr_q(30) xor lfsr_q(31) xor data_in(0) xor data_in(1) xor data_in(6) xor data_in(7);
    lfsr_c(2) <= lfsr_q(24) xor lfsr_q(25) xor lfsr_q(26) xor lfsr_q(30) xor lfsr_q(31) xor data_in(0) xor data_in(1) xor data_in(2) xor data_in(6) xor data_in(7);
    lfsr_c(3) <= lfsr_q(25) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(31) xor data_in(1) xor data_in(2) xor data_in(3) xor data_in(7);
    lfsr_c(4) <= lfsr_q(24) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(28) xor lfsr_q(30) xor data_in(0) xor data_in(2) xor data_in(3) xor data_in(4) xor data_in(6);
    lfsr_c(5) <= lfsr_q(24) xor lfsr_q(25) xor lfsr_q(27) xor lfsr_q(28) xor lfsr_q(29) xor lfsr_q(30) xor lfsr_q(31) xor data_in(0) xor data_in(1) xor data_in(3) xor data_in(4) xor data_in(5) xor data_in(6) xor data_in(7);
    lfsr_c(6) <= lfsr_q(25) xor lfsr_q(26) xor lfsr_q(28) xor lfsr_q(29) xor lfsr_q(30) xor lfsr_q(31) xor data_in(1) xor data_in(2) xor data_in(4) xor data_in(5) xor data_in(6) xor data_in(7);
    lfsr_c(7) <= lfsr_q(24) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(29) xor lfsr_q(31) xor data_in(0) xor data_in(2) xor data_in(3) xor data_in(5) xor data_in(7);
    lfsr_c(8) <= lfsr_q(0) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(27) xor lfsr_q(28) xor data_in(0) xor data_in(1) xor data_in(3) xor data_in(4);
    lfsr_c(9) <= lfsr_q(1) xor lfsr_q(25) xor lfsr_q(26) xor lfsr_q(28) xor lfsr_q(29) xor data_in(1) xor data_in(2) xor data_in(4) xor data_in(5);
    lfsr_c(10) <= lfsr_q(2) xor lfsr_q(24) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(29) xor data_in(0) xor data_in(2) xor data_in(3) xor data_in(5);
    lfsr_c(11) <= lfsr_q(3) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(27) xor lfsr_q(28) xor data_in(0) xor data_in(1) xor data_in(3) xor data_in(4);
    lfsr_c(12) <= lfsr_q(4) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(26) xor lfsr_q(28) xor lfsr_q(29) xor lfsr_q(30) xor data_in(0) xor data_in(1) xor data_in(2) xor data_in(4) xor data_in(5) xor data_in(6);
    lfsr_c(13) <= lfsr_q(5) xor lfsr_q(25) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(29) xor lfsr_q(30) xor lfsr_q(31) xor data_in(1) xor data_in(2) xor data_in(3) xor data_in(5) xor data_in(6) xor data_in(7);
    lfsr_c(14) <= lfsr_q(6) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(28) xor lfsr_q(30) xor lfsr_q(31) xor data_in(2) xor data_in(3) xor data_in(4) xor data_in(6) xor data_in(7);
    lfsr_c(15) <= lfsr_q(7) xor lfsr_q(27) xor lfsr_q(28) xor lfsr_q(29) xor lfsr_q(31) xor data_in(3) xor data_in(4) xor data_in(5) xor data_in(7);
    lfsr_c(16) <= lfsr_q(8) xor lfsr_q(24) xor lfsr_q(28) xor lfsr_q(29) xor data_in(0) xor data_in(4) xor data_in(5);
    lfsr_c(17) <= lfsr_q(9) xor lfsr_q(25) xor lfsr_q(29) xor lfsr_q(30) xor data_in(1) xor data_in(5) xor data_in(6);
    lfsr_c(18) <= lfsr_q(10) xor lfsr_q(26) xor lfsr_q(30) xor lfsr_q(31) xor data_in(2) xor data_in(6) xor data_in(7);
    lfsr_c(19) <= lfsr_q(11) xor lfsr_q(27) xor lfsr_q(31) xor data_in(3) xor data_in(7);
    lfsr_c(20) <= lfsr_q(12) xor lfsr_q(28) xor data_in(4);
    lfsr_c(21) <= lfsr_q(13) xor lfsr_q(29) xor data_in(5);
    lfsr_c(22) <= lfsr_q(14) xor lfsr_q(24) xor data_in(0);
    lfsr_c(23) <= lfsr_q(15) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(30) xor data_in(0) xor data_in(1) xor data_in(6);
    lfsr_c(24) <= lfsr_q(16) xor lfsr_q(25) xor lfsr_q(26) xor lfsr_q(31) xor data_in(1) xor data_in(2) xor data_in(7);
    lfsr_c(25) <= lfsr_q(17) xor lfsr_q(26) xor lfsr_q(27) xor data_in(2) xor data_in(3);
    lfsr_c(26) <= lfsr_q(18) xor lfsr_q(24) xor lfsr_q(27) xor lfsr_q(28) xor lfsr_q(30) xor data_in(0) xor data_in(3) xor data_in(4) xor data_in(6);
    lfsr_c(27) <= lfsr_q(19) xor lfsr_q(25) xor lfsr_q(28) xor lfsr_q(29) xor lfsr_q(31) xor data_in(1) xor data_in(4) xor data_in(5) xor data_in(7);
    lfsr_c(28) <= lfsr_q(20) xor lfsr_q(26) xor lfsr_q(29) xor lfsr_q(30) xor data_in(2) xor data_in(5) xor data_in(6);
    lfsr_c(29) <= lfsr_q(21) xor lfsr_q(27) xor lfsr_q(30) xor lfsr_q(31) xor data_in(3) xor data_in(6) xor data_in(7);
    lfsr_c(30) <= lfsr_q(22) xor lfsr_q(28) xor lfsr_q(31) xor data_in(4) xor data_in(7);
    lfsr_c(31) <= lfsr_q(23) xor lfsr_q(29) xor data_in(5);


    process (clk,rst) begin
      if (rst = '1') then
        lfsr_q <= (others=>'1');
      elsif (clk'EVENT and clk = '1') then
        if (crc_en = '1') then
          lfsr_q <= lfsr_c;
        end if;
      end if;
    end process;
   
end architecture Behavioral;



This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.
Dear Mohit,


I hope Xilinx will be able to help you out and thanks for letting us know!


Best Regards,
Arnaud
Dear Erik,

I just saw that this implementation is from xilinx. Sorry to bother you for this.

Thanks and Regards.
Dear Erik,

I think I have not been able to put my point across. Whatever codes of receiving or transmitting packets have been written in the application from the 4DSP side may not be complete is one aspect which has been correctly pointed out by the developer from 4DSP that error bits, collision bits etc. are not taken care, there is no problem with that. But whatever ethernet frame packeting has been done religiously follows standard document and I appreciate your group for that but when a CRC 32 does not look like CRC 32 but something different raises doubts in our minds.

So your  code in terms of ethernet interface can be used as building blocks which can be build upon further by us which is not the case in CRC 32 and I am not able to satisfy doubts raised here. To add further, this basic features if have some confusion should be supported at your end by at least better documented code or some reference code. There is nothing to hide in this at least

These two aspects are different and should be looked differently. Either some different concept is used for CRC 32 or there is some error which in our short span of study we have not been able to make out.

Anyways, I take your previous mails as your final reply.

Thanks.

Mohit
Dear Mhada,


the reference design ethernet interface is not meant to be used for a final application, only as an example to show how to operate the FMC board. It is a raw ethernet protocol without any security to make sure data transfers are always arriving correct. Therefore it is delivered as is and no documentation provided. A final customer application is expected to implement their own communication layer.




Best regards,
Erik
Dear Erik,

Thanks for the reply. Since there is no document available and since it does not give a standard result so we can remove this portion of the code and insert our own codes as every client wants an unambiguous and verified HDL description for the features implemented.

Many Thanks once again. It would have been better if the codes were slightly better documented.

Thanks and Regards.

Mohit


Dear Mhada,


this part of the reference design is delivered as is. no further documentation is available.


Best regards,
Erik
Dear Erik,

I have never said that it is not working but the implementation is not very clear to us is the problem as the results are not matching with any standard CRC 32 calculator so we want to know the approach used here as this will help us to us the code as it is with custom made PC side interface where similar such implementation needs to be done.

An implementation scheme or document related to this would be helpful.

Thanks and Regards.
Dear Mhada,


the CRC you are referring to is used in the ethernet transfer protocol and can be used as is. We have no reason to assume it is not working.



best regards,
Erik