Start a new topic

FMC104 - ZedBoard

Dear Forum:

Although I have been able to achieve operation of the FMC104 using only channels A and C at 100MSps, I still have several open issue and would I would like to speak with an engineer on the phone if at all possible.

My questions include:

1.  Given that the Zedboard only has LPC support, how does one (or is it required) reset the FPGAs after the AD9510 has been configured and the ADC clocks synchronized?  I am seeing issues with ADC coherency and while they could be caused by meso-syncronous clock domain crossing FIFO, I am unclear how the ADCs get reset after I configure the ADS9510.

2.  I found that channel E DDR bus violates the channel banking rules for the Zynq7020 as implemented on the ZedBoard with CHE_06 in bank34 and not bank35 with the channel E clock and other DDR signals.  Was this intentional or simply a byproduct of different hardware designs?  From my perspective I am not sure how to support BUFIO and IDELAYE/IDDR elements across banks.  Has 4DSP done this?  If so how?

3.  I dropped channels E and G from my initial design because of the above and also to reduce total logic.  Nonetheless, I have only been able to support IDDR INPUT OFFSET constraints for sampling rates up to about 130MSps.  I realize this may be more of Xilinx timing closure issue but given, again, that IO cannot adjust the set-up/hold window for the ADC data outputs because I cannot access the serial ports over the FMC-LPC interface, I wonder what rates has 4DSP been able to support using only the power-up ADC settings?  Given the Artix fabric, and my use of a 13-tap IDELAYE for the data bits and zero-tap for the corresponding clock signals, my attempts to set INPUT OFFSET constraints for timing at 210Msps (i.e. 750ps/750ps set-up and hold) and properly delay for the clock-forwarded IDDR timing window has not been successful.  Again, how fast a sampling rate has 4DSP obtained using Artix fabric?

Any other timing closure guidance would be appreciated as I have limited experience with this fabric and strategies for meeting IDDR input timing.



Dear Craig,

Could you please provide me the serial number of your board? I would like to check the exact hardware configuration you got. I am pretty sure your board support serial access to the ADC (writes only) since the SPI interface for the AD9510 can also access the ADCs.

Please note the following code in "fmc10x.vhd":


-- SPI Merging
-- on LPC carrier boards the ADCs can be configured in parallel (same settings
-- for all devices) through the following SPI signals:
-- * SPI Clock Line  = ad9510_sclk (connected to adc_sclk through 0R resistor)
-- * SPI Data Line  = ad9510_sdata (connected to adc_sdata through 0R resistor)
-- * SPI Chip Select = res_g2 (connected to adc_n_en<3:0> through 4K7 resistors)
res_g2_lpc : if (LPC_MODE = '1') generate
  ad9510_sclk  <= ad9510_sclk_i  when ad9510_n_oe = '0' else adc_sclk_i; --LPC connection
  ad9510_sdata <= ad9510_sdata_i when ad9510_n_oe = '0' else adc_sdata_i; --LPC connection

  adc_sclk    <= 'Z'; --HPC connection
  adc_sdata    <= 'Z'; --HPC connection

  adc_n_en    <= "ZZZZ"; --HPC connection
  res_g2      <= and_reduce(adc_n_en_i); --LPC connection
end generate;

This should give you some additional debugging possibilities. Regarding you questions:

1. If you need synchronous sampling across the ADC's you would indeed need to make sure the firmware supports that. From a hardware perspective the clocks are synchronous by default when the AD9510 is programmed and the ADC have fixed latency.

2. The FMC bus definitions does not always match with the application bus width or the number of I/O's on an FPGA bank. We have solved these issues in the
past by using MMCM of placing BUFG's after the BUFIO's and BUFR's.

3. I believe we have done LVDS 250MHz DDR.

Best Regards,
Hi Peter:

The S/N# is 2077 for this FMC104-2-2-1-1  card.  I did not realize that the AD9510 SPI lines could be shared and that would be very helpful if true.  It would also be helpful, if I could get a schematic of the FMC104 to more fully understand the board design.  Any possibility of that happening?  I think we are under and NDA but if not we could sign one.

Back to the issue of ADC clock coherency, I am concerned that after the ADC see invalid clocks during the time from power application until our host processor configures the ADC as this is done by the PS subsystem of the Zynq7020 and only uses the PL fabric to pass the signals through to the FMC104.  My concern is that the four different ADC chips may be left in some undefined state unless I am able to reset each device synchronously after the AD9510 is providing stable and synchronous clocks.  Do you agree that my concern is valid?

For channel E support on the Zedboard, are you suggesting that I use a separate MMCM to regenerate the CLK-E signal from bank 35 using a BUFG to feed the single IDELAYE/IDDR element for CHE_06 in bank 34?  If so, I have some concerns about making that work - I might need to feed a separate BUFR to feed the single IDDR element in bank 34 since that bank is used for channel A and channel C.

Thank you for your support,


Hi Peter:

With reference to your response to my question 3;

"I believe we have done LVDS 250MHz DDR."

Is that true for implementation on a ZedBoard Zynq 7020 with Artix FPGA fabric?  Or is that true with the FMC104 on some other host FPGA/3rd part host card?



It is not possible to provide a copy of the schematics. I do not believe your concern is valid. The ADC device does not need a reset. There is a reset pin on the ADC device but the only purpose it to reset the SPI register which come up in a defined and useful state after power up. SPI write access to the ADC devices works without giving a reset first.

Regarding the clocking scheme; the issue is that BUGIO and BUFR are regional resources and does not have enough span to reach all inputs. My best suggestions is:
Use MMCM instead of BUFIO/BUFR. The outputs of the MMCM can feed into BUFG. BUFG is a global resource and can reach all inputs.

I can see in our records that we have a reference design for FMC150 on the Zedboard, which used the same ADC device. I therefore believe we had that working at a sampling frequency of 245.76MHz.

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.