FMC104 - can't configure STATUS output to enable the internal oscillator
started a topic
almost 5 years ago
I am using an FMC104 connected to the FMC-LPC connector of a Zedboard. The Zynq 7020 is designed to use an AXI SPI peripheral to communicate with the 3-wire SPI interface of the FMC104 using 2.5V LVCMOS since the plan is to use LVDS 2.5V for the converters. I believe that I need to make the STATUS pin output of the AD9510 tri-stated so that the internal 100MHz reference oscillator is enabled. I believe that I can check this STATUS pin at a gold test point pad marked "STATUS". Is my understanding correct so far? To date, my attempts to configure the AD9510 and set the STAUS MUX register must not be working as I have never seen this test point go high. My transfers seem to complete without driver error and chipscope view of selected portions of the serial traffic appear to correct for operation in MSB-first mode but it is as if I am not communicating correctly. My understanding is that I need to operate the SPI interface in unidirectional mode with the SDIO pin of the AD9510 receiving the write data. The SDO pin, although active, is only available on the HPC portion of the connector for which I do not have access. Do I understand correctly? One thing that is curious to me is that the card powers up with a 288MHZ clock present on the external clock connector taken from OUT5 of the AD9510 and my programming of the AD9510 has had no effect on this signal. What is the source of this clock? If the on-card VCO were running wouldn't the AD9510 have to select CLK2 as input ? For now, I appear to be stuck.... I have S/N 2077. I would appreciate any help in confirming my AD9510 communication approach and/or information regarding how to enable the internal oscillator. Would it be possible to get a schematic for the FMC104? Thank you very much,
Craig Attention Forum: I found my problem and have been able to enable the internal oscillator and program the AD9510 as required. The problem was that my AXI SPI driver was configured to always raise the slave select line (CSB or AD9510_CS) between byte transfers. This signaling is referred to as "CSB stalling" by Analog Devices as decribed in the AD9510 data sheet. However, CSB stalling is only supported for byte transfers of one, two or three bytes and not in the streaming mode where more than three bytes are transferred consecutively. I failed to recoginze this point and had code my software to use streaming for much of the AD9510 configuration sequence. Once I re-coded to transfer three or fewer bytes per transfer call, the AD9510 was happy and I was bale to configure the chip correctly. Craig
Can you please post your latest question regarding DDR clocking on the FMC104?
almost 5 years ago
Sorry you felt left aside by the lack of answer, I estimated there was no answer required as you have fixed the issue the same day. The technical support is mainly processed from European Union and this is why we have a response time of 24 hours. We are training a colleague in Austin who will be handling support for America. He has already started and is doing great.
Please post your additional questions as per my request, I will personally follow up making sure you get an answer as fast as possible.