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data_valid signals on the FMC104, continuous run

[font=calibri]I am trying to alter the ml605_fmc104 firmware to do continuous signal processing on an input channel. I’ve combed over the VHDL code, done some ChipScope testing, and I think I found the piece of code / signal behavior that I want to change.[/font]
[font=calibri]Within the sip_fmc104_1 module, there is some control in place to read a set number of samples from the ADC. I believe the number of samples read is dictated by BurstSize. From the ChipScope traces, it looks like sequences of seven-64-bit words (28 samples) are read from the ADC FIFO. Then there is some waiting time, and then another 7 words are read. This continues indefinitely. There is a control signal named “adc0_out_dval” which is synchronized with the output data bursts, but it remains low after the BurstSize is met, and then the ouput data is no longer validated.[/font]
[font=calibri]I tracked the origins of the “adc0_out_dval” signal down into the “fmc10x_ctrl_inst” sub-module. The signal is named “chout_dval(7:0);” for control of up to 8 channels. The code in this module is very low level, and I can’t follow it easily. I was hoping you could advise me what to alter. I want the "chout_dval" signal to continuously validate the output data indefinitely, without regard to burst size. Again, this is so I can do continuous signal processing of a channel in a separate module.[/font]
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[font=calibri]Thank You,[/font]
1 Comment


the module fmc10x_io_buf_adc outputs a continuous data stream that is synchronous to the ADC sample clock. This data is then passed through a clock boundary fifo  fmc10x_cbfifo_16_64x256 that also de-multiplexes the data to 4 samples in parallel. That is because the default communication width withing 4DSP designs is  64 bits. Also we use a standard clock for communicating between blocks that is unrelated to the ADC clock. For both these reasons the output is not continuous.

In your case you can hook in on the 16 bits data coming from the fmc10x_io_buf_adc directly, the data is synchronous to the clock signal clk_ab_i.

Best regards,

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