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FMC110 PLL PFD frequency

What's the PFD frequency of the FMC110 PLL? For some reason the PLL is continuously locking and losing lock after its programmed with both internal and external reference clocks.


Dear Shant,

The PLL is managed by a chip called AD9517 and the PFD in there is clocked at 100MHz using an on board 100MHz reference. 100MHz seems to be the maximum. The reference design can be modified in order to use an external reference.

Best Regards,
Hi Arnaud,

I figured out the PLL lock issue, I was mislead by the settings in the ad9517_init_mem.mif file which configure the PLL to use the internal VCO by writing 0x02 to register 0x1E1. Apparently the clock chip is not wired to use the internal VCO and instead it uses an external VCXO. I would like to know what's the range of this external VCXO and the bandwidth of the filter that follows it.

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.