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How to control the FMC116 board and set important parameters?

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I have an FMC116 ADC Board on a VC707 Evaluation Kit. There are several problems to which I need answers.

1.      What tools do I need to program and control the FMC116 board? For example if I want to set the sampling rate, reference voltage, what tools should I use to set these parameters? Is it Stellar IP that I should use?

2.      After I set those important parameters with some tools, how should I transmit the data from the board to PC? Do I need to develop an application? What tools do I need to realize the communication between FMC116 (which is plugged on VC707) and PC?

3.      In chapter 8 of the “4FM_Get_Started_Guide”, I went through the contents in 8.1 and managed to retrieve some reasonable data. It seems that we only download a firmware to FPGA but does not download anything to the CPLD on FMC116. I want to know how the parameters (like sampling rate, reference voltage and clock) are set in this case.

4.      Besides I want to know how to make a firmware and a Stellar Definition File for a specific design.

It will be very nice of you if you can give me answers to those problems. What I am trying to accomplish now is to use FMC116 to sample and convert analog inputs into digital form, transmit the data to a PC and display it on the screen in real time. This sounds a very straightforward design, doesn’t it? Could you give some suggestions and guides?  Like what the design flow looks like and what tools I will need to accomplish the design?
Thank you very much


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Dear Sun wu
I am too the very beginner in this field so I thought to contact you.
I have FMC126 daughter board and the carrier board is DKXC5VMOD-1,virtex 5 FPGA board.
My project is too similar to you.I want to capture some analog signal and convert them into digital data and display them into PC or somewhere else.
How should I begin? and I dont understand one thing you have said in the early comment.
"[font=calibri][size=1.45em] It worked! I generated a bit file (although with many warnings together), downloaded it into the FPGA and then called the fmc116 application and finally managed to retrieve some reasonable data.[/size][/font]"
Can you please elaborate "[font=calibri][size=1.45em]then called the fmc116 application and finally managed to retrieve some reasonable data" ..
Please explain this in more detail.
Thank you



You should have source codes for serdes and bit align machine in your reference design. Basically it detects the edges of the data and adjust idelay to the optimal sampling point.

[font=calibri]Could you give some hints about how this bit align machine is designed? Is it possible to design it purely with the ISE project navigator? Could you recommend some references?[/font]
[font=calibri]Thank you[/font]


Our reference design does not use frame signals. When the trainning starts, the adc outputs the test pattern. The bit align matchine detects the test pattern and adjust the idelay to align the data and find the optimal sampling point. Once the trainning is done, all data is aligned so frame signal is not required.

[font=calibri]I found that the DCO and FR signal do not match the timing diagram in the LTC2175 data sheet when the sampling frequency is very high. This makes it difficult to align the data into the right form, doesn’t it? Is the “align machine” you mentioned used to solve this problem? Could you tell me more about this and also about the training you mentioned? Or could you recommend some references?[/font]


1) Our reference design uses a trainning to find the optimal sampling point. If the sampling frequency is changed, then the trainning has to be run again. Our design uses the serdes and idelay with the bit align machine. This design is suitable for the high sampling frequency. If the low sampling frequency is used, the idelay may be not probably working becuase the total delay of idelay is much smaller than the clock period. New design should be implemented for the low freuqncy. Using IDDR can be a good solution.
2) I'm sorry we cannot help you to understand the PLL configuration. Since we use 100MHz for the reference clock and 10 for R divider, the easiest configuration can be to change the R divier 1.
3) REFIN and CLKIN are connected as a differential pair as shown in Fig 9 in the User Manual.

[font=calibri]For the AD9517 on FMC116, there are two reference input pins (REF1, REF2). Could anyone tell me how the external reference or internal reference is connected to those pins? Is it connected to REF1 or REF2? Or is it connected to both REF1 and REF2 as a differential reference pair?[/font]
[font=calibri]I have some new questions regarding FMC116. It is about applying high sampling frequency.[/font]
[font=calibri]1.[/font]      [font=calibri]The clock signal I used was a clock signal generated by the VC707 board. I connected this signal to the “Clock In” of FMC116. Then I set some registers in AD9517 (mainly 0x1e1, 0x192, 0x198, 0x232) so that this clock signal could be routed to the clock input of the four LTC2175s on the board. I tried retrieving and plotting data and it worked. But as I increased the frequency of this clock signal, the board became unable to work well. Before the frequency reached 18MHz, the data plot was very clean and clear. But as the frequency became larger, more and more glitches appeared in the data plot. When the frequency was 20MHz, the data plot was just like noise. But the maximum sampling frequency could be as high as 125MHz, couldn’t it? What may be the reason?[/font]
[font=calibri]2.[/font]      [font=calibri]One reason for the above problem I think may be because high frequency clock signals could not be transmitted through the cables onto FMC116 very well, so I tried using a 10MHz clock signal from VC707 as a reference signal and using the internal VCO and PLL on AD9517 of FMC116 to generate an on-chip high frequency clock signal. However the configuration seemed pretty complicated.  Could you tell me which registers I need to set to realize this configuration which can generate high frequency clock signals with a low frequency reference clock from VC707?[/font]


1. You can only write one registers at the same time. SCLK is needed only when CS is enabled. So, I will say there should be no SCLK cycle is needed as long as ADC device detects the start and stop signals from CS. You can set N_CS to 0 and leaves it. It will be connected to one of CS only when the software communicates. Otherwise, it will be 1. If you see how it communicates in the software. It will be more clear.

2. When arm is asserted, ADC becomes ready to capture data and trigger tells ADC to start grasp the data and store it to the fifo. The ADC will capture the data at the sampling frequency. I think if you see a vhdl code "\4dsp\Common\Firmware\Extracted\xxx_xxx_fmc116\star_lib\sip_fmc116\fmc116_ctrl.vhdl", you can understand it much better.

[font=times new roman][size=4]Hi Dear Kyu,[/size][/font]

[font=times new roman][size=4]Sorry for not having expressing the question well.[/size][/font]

[font=times new roman][size=4]1. Explanation to question 4: First I’d like you to look at Figure 11 in the FMC116_FMC112_user_mannual. There are three ports: SCLK, N_CS, SDIO which are connected to CPLD and we can program the device through these three ports, which are also connected to CTRL(0), CTRL(1) and CTRL(2) on the FMC connector.  Then I’d like you to look at Figure 12, which shows how to write some data into a register. You can see that N_CS is “0” for 24 cycles of SCLK. I just want to say that, N_CS is “0” for only 24 cycles in this case, right? It cannot be “0” for 48 cycles to write TWO registers, can it? We can only write one register a time, can’t we? If so, there must be some SCLK cycles between two sequential writing operations during which N_CS is “1”, right? I just want to know how many cycles there has to be between every two operations.[/size][/font]

[font=times new roman][size=4]2. I am still not clear about the trigger signal and clock signal. According to your answer, Trigger tells the ADC to capture the data. Then it is the trigger signal which decides the sampling frequency rather than the clock signal, isn't it? Then what is clock signal used for? Are there any constraints or relations between the frequency of trigger signal and that of clock signal?[/size][/font]

[font=times new roman][size=4]Xun[/size][/font]


Many questions are refering to the data sheet. I think the manufacturer can give better answers.

1. Our user manual says input voltage range is 2Vpp. We are following the datasheet. You may need to contact the manufacturer to have a bette answer.
2. Those signals are connected to ENC pins. To set the sampling frequency, I think this depends on how you implement it. We configure it with using the software because it's easy for customers to modify it. For the register maps, you can see in the datasheet. For our constellation register map, you can find it "firmware folder/output/xxx_xxx/Src/sip_cid/cid_package.vhd"
3. In our reference design, what you need to do is to provide the external clock and trigger and run the software application in the external clock mode.
4. Can you explain me more about this question?
5. You can also get it from the datasheet. The datasheet says the min clock period is 40ns for Write Mode and 250ns for Readback mode.
6. Yes. I think all 4 clock have the same frequencies in the reference design.
7. Trigger is a signal that tells the ADC to capture the data.

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Hello dear everyone,

I am now thinking about controlling the FMC116 using purely hardware. I am trying to build an initialization circuit for it. And there are some questions I want to solve first.

1.      What is the voltage range of the ADC on FMC116? Is it decided by REFH (Pin 6, 7) and REFL (Pin 8, 9) of the LTC2175-14 ADCs on the board? If so, what voltages are connected to those pins on FMC116 board? Is it possible to use external reference voltages?

2.      It looks like the frequency of the signal connected to ENC+ (Pin 17) and ENC- (Pin 18) of [/font][/size][/font][font=calibri][size=1.35em][font=times new roman][/size][size=3]LTC2175-14[/size][size=1.35em] decides the sampling rate, is this right? Are those two pins connected to clock signals coming from AD9517? If so, how are they connected? How can I set this sampling frequency purely through the SPI communication bus (without software)?  Could you offer the corresponding timing diagrams and register map for this?

3.      If I want to use external clock signal, I should first set “CLKSRC” of “CPLD_REG0” to be 00 and connect the [u]clk in[/u] on FMC116 to an external clock signal. What is next step I should do? Are there any other registers that I need to set?

4.      How many clock cycles should be left between two sequential SPI commands transmitted to CPLD?
[font=calibri][size=1.35em][font=times new roman]5.      What is the largest possible frequency of the SCLK (CTRL(0)) signal that acts as the command clock?[/font][/size][/font]

[font=times new roman]6.        [size=3]It seems that [/size][/font]the four [font=calibri][size=1.35em][font=times new roman]LTC2175-14 ADCs have four different clock signals. Is it possible to let them share one clock signal or make those four clock signals identical?[/font][/size][/font]

7.      I am feeling a little confused about the "clock" signal and "trigger" signal on FMC116. Could you explain to me the differences between them?
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Dear Xun,
Please contact your sales point or contact [email][/email].
We can offer you a training of 1, 2 or 3 hours where we will be able to help you out in details. You could also purchase a engineering support contract where you will get detailed answers to your questions.
You can also follow the steps in the 4FM Getting Started Guide, they are covering creation of a firmware or stars. You can refer to the ML605 material which is similar.
Best Regards,
[font=calibri][size=5]And another thing is that, in the reference design for FMC116 and VC707, the 16 channels are not synchronous. Now I really want to modify this design so that the 16 channels can sample and acquire data simultaneously. I know this modification may be complicated. But could you give me some suggestions as how I should start? What corresponding modification do I need to make to the software for this design?[/size][/font]