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How to control the FMC116 board and set important parameters?

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Hello,

I have an FMC116 ADC Board on a VC707 Evaluation Kit. There are several problems to which I need answers.

1.      What tools do I need to program and control the FMC116 board? For example if I want to set the sampling rate, reference voltage, what tools should I use to set these parameters? Is it Stellar IP that I should use?

2.      After I set those important parameters with some tools, how should I transmit the data from the board to PC? Do I need to develop an application? What tools do I need to realize the communication between FMC116 (which is plugged on VC707) and PC?

3.      In chapter 8 of the “4FM_Get_Started_Guide”, I went through the contents in 8.1 and managed to retrieve some reasonable data. It seems that we only download a firmware to FPGA but does not download anything to the CPLD on FMC116. I want to know how the parameters (like sampling rate, reference voltage and clock) are set in this case.

4.      Besides I want to know how to make a firmware and a Stellar Definition File for a specific design.

It will be very nice of you if you can give me answers to those problems. What I am trying to accomplish now is to use FMC116 to sample and convert analog inputs into digital form, transmit the data to a PC and display it on the screen in real time. This sounds a very straightforward design, doesn’t it? Could you give some suggestions and guides?  Like what the design flow looks like and what tools I will need to accomplish the design?
Thank you very much

Xun
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Xun,


1) Our reference design uses a trainning to find the optimal sampling point. If the sampling frequency is changed, then the trainning has to be run again. Our design uses the serdes and idelay with the bit align machine. This design is suitable for the high sampling frequency. If the low sampling frequency is used, the idelay may be not probably working becuase the total delay of idelay is much smaller than the clock period. New design should be implemented for the low freuqncy. Using IDDR can be a good solution.
2) I'm sorry we cannot help you to understand the PLL configuration. Since we use 100MHz for the reference clock and 10 for R divider, the easiest configuration can be to change the R divier 1.
3) REFIN and CLKIN are connected as a differential pair as shown in Fig 9 in the User Manual.


Thanks,
Kyu
[font=calibri]Kyu,[/font]
[font=calibri]I found that the DCO and FR signal do not match the timing diagram in the LTC2175 data sheet when the sampling frequency is very high. This makes it difficult to align the data into the right form, doesn’t it? Is the “align machine” you mentioned used to solve this problem? Could you tell me more about this and also about the training you mentioned? Or could you recommend some references?[/font]
[font=calibri]Xun[/font]

Xun,


Our reference design does not use frame signals. When the trainning starts, the adc outputs the test pattern. The bit align matchine detects the test pattern and adjust the idelay to align the data and find the optimal sampling point. Once the trainning is done, all data is aligned so frame signal is not required.


Thanks,
Kyu
[font=calibri]Kyu,[/font]
[font=calibri]Could you give some hints about how this bit align machine is designed? Is it possible to design it purely with the ISE project navigator? Could you recommend some references?[/font]
[font=calibri]Thank you[/font]
[font=calibri]Xun[/font]

Xun,


You should have source codes for serdes and bit align machine in your reference design. Basically it detects the edges of the data and adjust idelay to the optimal sampling point.


Thanks,
Kyu
Dear Sun wu
I am too the very beginner in this field so I thought to contact you.
I have FMC126 daughter board and the carrier board is DKXC5VMOD-1,virtex 5 FPGA board.
My project is too similar to you.I want to capture some analog signal and convert them into digital data and display them into PC or somewhere else.
How should I begin? and I dont understand one thing you have said in the early comment.
"[font=calibri][size=1.45em] It worked! I generated a bit file (although with many warnings together), downloaded it into the FPGA and then called the fmc116 application and finally managed to retrieve some reasonable data.[/size][/font]"
Can you please elaborate "[font=calibri][size=1.45em]then called the fmc116 application and finally managed to retrieve some reasonable data" ..
Please explain this in more detail.
Thank you
Dipen

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