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Simultaneous capture of multiple channels

Hello,

I added chipscope to the VC707 reference design (I added adc0_out_data and adc1_out_data to Chipscope Trigger ports) but then the design has Timing Problems in 156.25 MHz Clock Domain.

I want to check how much phase uncertainty I get when I sample the same signal (Signal Generator connected to a Splitter, connected Channel A + Channel B) on two channels (without using the calibration package).

Do you have a tip or a working design that could help me?

Or, is it possible to sample multiple channels simultaneous with 4FM FMC Analyzer Application?

Best regards,

Philipp

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.
Dear Philipp,


Please create new topics if you need more information.


Best Regards,
Arnaud




Arnaud,

thank you. I will try it with Vivado. Maybe I get better results then.

Best regards,

Philipp
Dear Philipp,


Please let me know if there is anything I can do for you before to close this topic.


Best Regards,
Arnaud
Philipp,


1 channel mode is using the four ADC channels and rebuilding the final buffer keeping an ENOB as per the e2v datasheets. So yes, we do have everything spot on for both digital (in the FPGA) and analog domain (in the E2V chip). I believe the main difference would be the input mux settings in the e2v chip.


The package does not directly support four channel mode but the algorithm to have the four channels compensated for offset, gain and phase is in there. We do connect an RF signal on A and the e2v chip output one quarter of the samples on every channel. For the offset we leave everything unconnected and make sure the average of the noise is around ADC mid-scale. For the gain we are using channel A as reference and making sure power FFT of the other signal has the same fundamental power. For the phase we are actually looking at the signal reconstructed over the four channels (in one channel mode) and compensate in order to reduce the interleaving spurs.


Typically we implemented the whole scheme without to use chipscope. We have looked at buffer saved by our FMC12xApp.exe and first analyzed the buffers with Matlab, came up with a calibration method and implemented that in software.


And of course it is pointless to try to tune the analog domain in the e2v chip before having the bus aligned properly on the digital domain. This block doing that in the firmware is the bit align machine.


Best Regards,
Arnaud



Hello Arnaud,

does the calibration package provide synchronous data in 4 channel mode as well?
Do you apply a RF testsignal to all four channels to calibrate the Phase (and gain)?

Best regards,

Philipp
Dear Philip,


Also I would like to repeat that we have a calibration package available able to get you started in 1/2 channel modes (5Gsps and 2.5Gsps). The package consists on a synchronous firmware, modified software as well as the analog domain calibration algorithm in source code.


Best Regards,
Arnaud
Dear Philipp,


I am not sure there is much I can do here. As explained we do not use chipscope much around here. I would myself create a Webcase with Xilinx and asking them if they have guidelines on how to use chipscope and create ILA/ICON core easier for the tool to place and route!


Best Regards,
Arnaud
Arnaud,

Thank you for this Information. I changed inx_stop and implemented Chipscope, but I have still timing problems in the fifo readout domain (where chipscope is connected).

Dear Sir,


Was the information sufficient? Can I proceed with closing this topic?


Best Regards,
Arnaud
Philipp,


I think you are right, inx_stop should be asserted when it is not connected to the output. That should be sufficient. Our designer decided to block data flowing out of the FMC126 star instead. I cannot come up with which path is better. I also don't know much about your application but you might anyway want to interleave the data, getting rid of the router and replacing that with a merger anyway.


Your second question is exactly what was done by our designer. He made sure that data of the four channels remains in the FMC126 star internal FIFOs. Then he would take data from one channel, then the second one. But this time the channels are related in a time point of view.


Does that help?


Best Regards,
Arnaud
Arnaud,

You are talking about in0_stop, in1_stop, in2_stop, in3_stop signals, that are generated in router_s5d1.vhd?

Is it possible to stop all channels at one time and get all data later before restarting?

Best regards,

Philipp
Philip,


I am simply telling you sip_routers star are eating input data not connected to an output and this is the first thing we has to do in order to have any coherency between the channels. We added a keep data flag in the FMC126 star, causing data to stay in the internal FIFOs.


The SYNC pulse is done by the CPLD, a software command is sent to CPLD, generating these pulses.


Best Regards,
Arnaud
Hello Arnauld,

thank you for your reply.

>The firmware is not synchronous on the reference design.

Well, I don't need synchronous sympling. But just a question: how do you run the sync pin of FMC126? The appropriate code is out-commented in ev10aq190_quad_phy_v7.vhd:614

--sync_out : obufds (Not used on the VC707, signals are mapped to GPIO_LED 6 and 7)
--port map (
--  i  => sync_pls,
--  o  => sync_p,
--  ob => sync_n
--);

>Typically in the firmware is a data router and the data router eats any sample flowing from an input (source) not connected to an output (destination).

But if I connect Chipscope to adc0_out_data, adc1_out_data, adc2_out_data, adc3_out_data in fmc126_if.vhd, the Output is connected.

Best regards,

Philipp
Dear Philip,


Can you let me know if the pointers were good enough? Are you able to move forward?


Best Regards,
Arnaud