Start a new topic

FMC125 to Xilinx system

Hello,

I am trying to get data from the FMC125 into a kc705 development board.
I have a custom design which needs to use this data. I am able to capture data using the ethernet port, but I would like to pass this data onto my design... possible with a microblaze.

What would be the simplest way? I have tried looking at the examples provided, including AN002, but have run into several problems.

Can you please suggest a method in which I could get data from the card into my system, maybe through a fifo?

Thanks,
Rakesh

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.
Great news Rakesh!



Hello Arnaud,


The problem was with the ILA sampling!
I have increased the sampling frequency to two times the rate of axi... and i get correct output!


Regards,
Rakesh
Dear Rakesh,


You must be on the right track, this spike makes me believe this is a digital domain bit error. In our software/firmware we are indeed making sure the bits in the databus are aligned by delaying faster signal..


The AXI master core is indeed sweet but yeah as you understand, not existing for ISE.


Best Regards,
Arnaud
Hello Arnaud,


I will check the timing reports more carefully. I had some violations when i moved the ucf file to the XDC file needed by vivado. Unfortunately I cannot find the JTAG aXI master for ISE to run with the ucf file.


I ran the ramp test for the ADC0 and I notice that one of the bits is out of phase by one clock cycle? There are registers EV8AQ160_QUAD_PHY_INC and DEC which indicate that i can control some delays.... I will look at them to see if i can fix this problem.


Attached are two pictures..


Thanks for your help and any input on this problem will make my job a bit easier.


Regards,
Rakesh
Dear Rakesh,


According to your report, the issue on on your firmware. This is far beyond standard technical support but you should make sure to check timing reports from ISE. If ILA cannot run fast enough, you should see that in the timing report. Maybe the ILA peripheral makes more difficult routing and some timing constraints are missing. It could be as simple as you not using the right clock for ILA. It should be on the same clock boundary as the samples.


I hope that helps,
Arnaud
Adding the boot script since I am not allowed to attach more than 4 files..


Regards,
Rakesh
Hello Arnaud,


Thank you for your reply.
After a lot of struggle, I have finally managed to get the ADC to capture date using the XILINX ILA.


But there seems to be some noise in the data I have captured. I have attached two sets of figures, one from the data obtained from the MAC engine and the other one from the XILINX ILA data collector.


The Xilinx Data seems to be a little corrupted. I think there are more repeated values in the data from the ILA when compared to the MAC engine data? Is this because the ILA cannot sample fast enough? Or is there something else I need to do?


I have also attached the boot script I use to configure the ADC. I am using only ADC0 and the setup is very similar to AN002.


Thanks,
Rakesh
Dear Sir,


Was the information useful? Can I do anything else before closing this topic?


Feel free to open any other topics if you need to do so.


Best Regards,
Arnaud
Dear Sir,


Step by step! You first want to run FMC12xApp, this application is configuring the whole integrated circuit set, acquire sample and save the samples to hard disk.


The complete material for AN002 is found there : C:\Program Files (x86)\4dsp\4FM Core Development Kit\StellarIP\Training Material\AN Materials\AN002\Src


I hope that helps,
Arnaud
Hello,

Just making an update on how i interfaced the ADC125 to my xilinx system.
I followed AN002 and replaced the mac_eth master by a jtag_axi_tx generator as shown in the pdf.

I had problems generating the IPs for the fifos used and had to struggle a bit with vivado, but finally i got the simulation to work and i am able to perform the correct writes to enable the ADC 0 and ADC1 to send me data..

I also noticed that the AN002 document specifies that for hardware implementaiton, the init script is different from the one used for simulation(addr.coe and data.coe)... is it possible for me to generate the hardware init script for FMC125 on KC705 from the C application file provided with AN002 example?

Or should I go through the steps performed in 252_kc705_fmc125 C application whcih interfaces with the ethernet and figure out the right commands that I should input from the AXI master to get the ADC to work on the KC705 board?

It would be of immense help if you can point me to the direction where i can generate these tcl files, i have manually tried modifying them, but cant get the ILA to capture data yet.


Thanks,
Rakesh