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FMC125, not able to read the FMC125 configuration registers

Dear Madam/Sir,

I am currently interfacing the VHDL implementation of the sip_fmc125 vhdl module directly from Xilinx ISE. I have some questions since I am not able to get the right response from my FMC125 device while trying to read the state of all its configuration registers.

-First of all, I try to read out the FMC125 registers using the cmd_in and cmd_out wormholes. However, I never got the cmdout_val bit high, neither the right values on the cmdout port. To show how I interface the FMC125, I added a timing diagram as attachment to this topic. I assumed the cmdclk should only be high once per read operation. Is that correct? If not, what will be a valid clock speed for that?

-Can I rely on the fact that all registers are programmed to a certain default value up-front?

-What is the maximum speed I can configure the registers (write cmd) of the FMC125 board? Does the VHDL implementation buffer the write operations in case they are provided at a rate of e.g. 150 MHz? I have not been able to figure that out reading the documentation.

-Reading the manual ('FMC122/FMC125/FMC126 User manual', page 10, top) I noticed that the CPLD should not be reprogrammed or erased. However, If I would like to use the on-board VCO as a sampling clock, we do need to reprogram this CPLD device by reprogramming its REG0.  Can you confirm I interpreted that part of the documentation correctly?


Thanks for your reply.

Yours sincerely,

[img width=640 height=223]http://homes.esat.kuleuven.be/~tredant/fmc125_timing_diagram.png[/img]

Tom
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Dear Tom,


StellarIP is able to generate a design for many hardware platforms and the reference software is completely programming the chip set through the reference firmware.


Some of the default value are programmed by the firmware, but only a few subsets, the reference design does not get alive without "life support".


The reference application works for both internal and external clock mode, this is an application argument translating down to hardware write.


You will indeed not find all the information in the documentation because everything is complex and this is why we are providing software/firmware source code which brings the hardware up at his full specs.


Most of the "secrets" are going to be revealed by the software application which configures all the ics in a state they can be used!


Best Regards,
Arnaud
Dear Arnaud,

thanks for your reply. I already experimented with the Stellar IP last week. I was able to instantiate the sip_fmc125 ip block. However, there are still some inputs I do not know how to connect. e.g. the cmdclk_in, the cmd_in and the cmd_out...

Is there a particular IP block I can take from the library to connect to these ports in order to implement the configuration.

Regards,

Tom
Dear Arnaud,

I have another question. I noticed that there is not .dsn file in the folder 104_ml605_fmc125.  What might be the reason for that?

Regards,

Tom Redant
Tom,


StellarIP generates a complete firmware project with the stars all interconnected properly and SD/CD documentation should help along with the simulation.


The ML605-FMC125 firmware was released in 2011, before the new StellarIP was existing so it is based on an xml and sdf file. Please check the 4FM Getting Started, 4FM_Get_Started_Guide.pdf in C:\Program Files (x86)\4dsp\4FM Core Development Kit\Documentation. There is a chapter about importing legacy design, This is chapter 8 I believe. The old design files should be converted to both a .dsn and a .tclib library


Best Regards,
Arnaud



Dear Tom,


Please let me know if we can consider this issue as resolved, with your permission I will close this topic.


Best Regards,
Arnaud
Dear Arnaud,

based on your input and some further experimenting in VHDL I figured out how to configure the FMC125 by means of the cmdin and cmdin_val lines. I was able to configure the following registers to the following values:

addr: x0000, data: 00000000000000000000000000000000
addr: x0001, data: 00000000000000000000000000001111
addr: x0002, data: 00000000000000000000000000000000
addr: x0003, data: 00000000000000000000000000000000
addr: x0004, data: 00000000000000000000000000000011
addr: x0010, data: 00000000000000000000000000000000
addr: x0011, data: 00000000000000000000000000000000
addr: x0600, data: 00000000000000000000000000000110



However, I was not able to program register x1600. This is because it uses the I2C protocol. The other registers I programmed do not use the I2C protocol. Do I first need to set the PRER-register of the SC18IS602B_CTRL entity before I am able to use the I2C protocol? Can you give me further explanations on this so I can also program the final register x1600?

I think if you can provide me an answer to this final question, we can close this thread.

Regards and thank you.

Tom
Dear Tom,


Ok, so you are able to exercise the command bus and you are unable to program register at address 0x1600, which is CPLD register number 0.


Would you be able to details what does not work? Is both reading and writing failing?


Can you please run the reference design and make sure everything works one of the reason of having the CPLD not answering would be the CPLD not being programmed.


Thanks,
Arnaud





Dear Arnaud,


thanks for your reply. I was able to run the reference design. Moreover, I was able to see the digitized signal on my computer. So we can conclude the CPLD works. Moreover, I was able to do that without actually needing an external clock. I can assume that the internal reference and internally-generated clock works well as well.


Now, I would like to interface the sip_fmc125 directly from my xilinx ise environment, embedding it in my custom application, moreover, configuring it directly from my FPGA. Everything goes well. I am making progress with my design. However, I am not able to select the internally generated clock using the internal reference.


This is how I try to configure the A/D to select its interally generated clock (using internal reference):


First I configure x0600 by the following value.
addr: x0600, data: 00000000000000000000000000000110


I verify whether this x0600 has really been programmed by reading its value after its write operation. I can conclude that x0600 is well-programmed.


Now, I need to write x1600. This is the only 'special' register I need to write since it uses the I2C protocol to interface with the CPLD. The other registers are actually part of the RTL-blocks running on the FPGA. These do not use the I2C. This is the data I want to prgram:


addr: x1600, data: 00000000000000000000000000011110.


Reading the manual I see that 110 for CLKSRC means 'internal clock, internal reference'. That is the value I want.
Additionally, I chose 11 for SYNCSRC meaning 'No Sync'. I think the A/D does not wait for a trigger doing this. Anyway, I think that the actual value of this SYNCSRC does not matter.


Reading x1600 I see all zeroes. I am clearly doing something wrong. Not sure whether this happens while writing or reading.


I think this has something to do with the I2C interface. Maybe the I2C interface assumes that the cmd_clk has a particular value. Moreover I think that this value should be stored in the PRER-register of the SC18IS602B_CTRL block.


Arnaud, reading the 'FMC125 Star Quad 8-bit 1.25 Gbps ADC Daughter card' pdf documentation, which I consider as a datasheet for the 4DSP VHDL-module sip_fmc125, I should have enough information to interface the board and its VHDL firmware. However, to my opinion there are still too many question marks I needed to fill in myself, e.g. timing diagram of the read and write operations, the value I need to write to the PRER-register... Since I ve been investing a lot of times in this A/D over the last week I was able to figure out everything reading through the VHDL-files itself. However this I2C is still an open issue.


I see two possible outcomes here:
-either we can have a phone call on this issue,
-either you have some kind of stripped-down runnable model of how to write register x1600. Writing this register is not as straightforward as writing the others in my opinion.


Regards,


Thank you,


Tom
Dear Tom,


The problem here is that the reference design just works. Now you are trying to modify/port the reference design, which is an integration task and this is not technical support anymore. I will not be able to get in depth like that anymore unless there is a extended technical support contract in place, especially because all the information is there. Maybe I can ask a sales colleague to get in touch with you in order to discuss that further?


- Look at Figure 10 in the FMC12x User Manual, this shows everything is I2C but some of the I2C addresses are translated to SPI, the CPLD is not having i2c
- Look at chapter 4 in SD0059 document and compare that to the address you wrote. There you understand you have only wrote/read register in the fabric and nothing through the bridge.
- Look at the SD0059 document, page 17, PRER definition, there is a small mistake 125MHz should read cmd_clk, just to be sure set your command clock to 125MHz, and see if it helps, that's a quick test, quicker than even write about it. I don't think the problem lays here. The default value in the FMC125 star are fine up to a 1:4 error I believe


Now more interesting, in the documentation, "SC_A" and its definition "Global Address pin configuration on FMC bus (GA1 and GA0). Defines the I2C slave address on the I2C-to-SPI bridge". In your write sequence I don't see you configuring that address, implicitly you are using default GA value of 00. Now looking at the Xilinx evaluation board schematics (and FMC12x FMC pinout) you will see that KC705 has GA1:GA0=b00, VC707 has GA1:GA0=b00 and ML605 has GA1:GA0=b10


This directly relates to table 7 in the FMC12x user manual document.


Maybe this is not the actual problem but this will already help as not writing this register on ML605 (or any FPGA board with GA pins not 0 ) will prevent any i2c communication. Fact is that I found this information by reading the documentation, SD and user manual ( I was not involved in the FMC110 design at all ). I asked the following questions to myself:


- What the communication looks like? The answer is on FMC12x user manual chapter 5
- What could prevent i2c communication? The answer is generally wrong address, simple assumption by experience, the other one could be i2c speed indeed.
- What should be the address? Looking at the user manual table 7, it is clear GA is involved.
- What is GA? Google tells that this is global address topology pins.
- How can I make sure the FMC125 star uses the GA pin matching my hardware? Well there I have search the SD documentation for GA0 text and there I found SC18IS602B_CTRL_SC_A register description.
- How do I know which value I should use? Well using FMC pinout in the FMC12x user manual and your carrier documentation/schematics, or looking into main.cpp of FMC12xApp software application; This application supports many carriers the generic way.


I hope that helps,
Arnaud





















Dear Tom,


Can you please report back, did this extra information help you out?


Can I close the topic?


Best Regards,
Arnaud
Dear Arnaud,

thanks for these insights. I was able to figure it out based on some hints you gave.

Thank you Arnaud,


Tom
This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.