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FMC126: going from 4 channels (1.25 Gsps) to 2 channels (2.5 Gsps)


we are using "kc705_fmc126.bit" file to program the FPGA Kintex 7 using impact(Xilinx)
and then using Fmc12xapp.exe to sample and acquire data.

How do we make the configuration change
1) sampling speed 2.5 Gsps with 2 channels
2) increasing burst size


Dear Sir

1) This is not a configuration change but important firmware/software changes. E2V, the chip manufacturer provides an application notes on how to use their chip in this mode. Alternatively, you can purchase the calibration package for FMC126 which will get up and running quickly. You can contact for more information about this product, the calibration package for FMC126.

2) There is a function in the reference software application, FMC12x_ctrl_configure_burst() doing that. The buffering in the reference software is minimalist; you will only be able to get a couple of snapshots, a few kilo samples and this is not suited for streaming application. This is because the lack of buffering on to external memory as the DDR3 on KC705.

Both of these points will require an important amount of work, especially the first one if you decide to not purchase the calibration package.

Best Regards,


thanks for the reply.

What can I do to get the relative sample numbers for different channels.
I noticed that there is a random delay between any 2 channels when you compare the data.

For eg. the 1stt sample on adc1 is sampled at the same time as the nth sample of adc0, I want to know n?

(Sales quoted the Calibration kit to be 3k USD much higher than what we expected)

Hello Vins,

3k$ might look expensive, but I assume you guys will spend around 90 man days ( if you get skilled engineers ) to get it right including a lot of ping pong with E2V assuming E2V agrees to help you out.

There are many other things, clock domain crossing, sample accurate triggering, etc.. People tend to not anticipate those even if this is the tougher aspect of a firmware design.

You will need:

- Sample accurate triggering.
- Synchronous acquisition.
- Tuned data buses (IODelay calibration) ( the ADC bits should be synchronous in the digital domain ).
- Calibrate E2V chip for phase.
- Calibrate E2V chip for offset.
- Calibrate E2V chip for gain.
- Reconstruct the final signal.
- Have a well defined test instrumentation ( which signal generators and which filters ).

Of course everything is possible as you have source code of everything (software and firmware), the documentation and you can request the calibration application notes from e2v.

Unfortunately I cannot do more for you. Feel free to post on the forum if you have any problems running the reference design. As explained to you, the data router eats data, the amount of data eaten will depend on the Windows non real time feature so the channels are not synchronous by design so this is not a problem, this is simply how it is.

Thank you for your understanding and best regards,

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.