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FMC125 Synchronization of 4 channels and 4 boards

Hi there,
We really need your feedback on this...

Our system requires the 4 channels in one FMC125 to be sampled at the same time (synchronized).  Later, we would require to synchronize 4 FMC125 boards.

Unfortunately we cannot yet synchronize the 4 internal ADCs on the e2V chip on the FMC125 mainly because the SYNC input has special timing requirements (@2.5GHz) based on their App. Note 1083B.

The App. Note (fig.1.) states that the SYNC pulse has to be registered at 2.5GHz (with a D flip-flop) and of course paths of CLK and SYNC signal have to have the same delay[size=3][font=times new roman,serif][/size][size=12pt][color=#1f497d][/size][size=2][font=calibri,sans-serif][/size][size=11pt]. :o [/size][size=2][/font][/size][size=12pt][/color][/size][size=3][/font][/size]
1. The SYNC  on the app note (fig. 1 ) is an e2v input pin, but the FMC125 has 2 components in that path before reaching that input pin: a 1:2 any level to LVDS buffer and a LVDS mux. (fig. 2) We need to know the propagation delays inserted by them. Could you tell me which components are these? Or the total delay from the SSMC connector to the e2V chip for both the CLK and the SYNC inputs?

2. The flip-flop has a LVPECL differential output that will be connected to ext TRIGGER input of the FMC125 (that goes to the 1:2 buffer) (fig. 2 ) but with some changes as by default it accepts LVTTL.
There are different ways to terminate a LVPECL signal either using both or just one of the I/O differential pair, usually providing a reference voltage, therefore we need more details about placement of extra components to be LVPECL compatible or should we send the boards back to you? Moreover I guess that the 1:2 buffer already has internal 50 ohm resistors?

Thanks a lot!!

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.






[quote]a. I understand then that you have not tried the calibration package in four channel mode?[/quote]
True, the calibration package is using one channel mode, but that can only be successful when the channels are aligned.


[quote]b. have you seen the training patterns aligned after a SYNC pulse in one (or four) channel mode, in either the reference design or the calibration package?[/quote]
No, it was confirmed by E2V that the SYNC pulse has no effect on the training pattern.


[quote]c. It is still not clear to me whether I have to provide that SYNC pulse as described in E2V app. note? We need to be clear on this as we are making the PCB suggested in that app. note in order to provide the correct SYNC pulse, but maybe this is not needed with your calibration package?[/quote]
The device need a SYNC pulse, but the FMC125 offers different ways to apply the sync. Our calibration package applies 100 sync pulses from a local source (CPLD). From the FPGA would be an option if the carrier board routes the signal. See errata attached, I am not sure if the 8-bit device has the same errata, but the same strategy works.

[quote]d. Do we have to perform the calibration of the ADC every time the it is turned on?[/quote]
There is a difference between synchronization and calibration. It looks like you're still stuck on synchronization. Both need to be done after power-up. Calibration is about fine tuning phase, gain, and offset between the channels and once optimal values have been found re-calibration is not required. Instead the values can be used directly. Significant changes in sampling frequency or temperature requires re-calibration. Our calibration package contains routines to calibrate the channels, but this might not be needed in your application if your only goal is synchronization.


Best Regards,
Peter
Hi Peter,

[i]"..How do you collect samples? Our reference design is grabbing samples from one channel at a time[/i]..."

I added a ChipScope module to your reference design and fed it with the respective data. (I did not modify your code, just added extra blocks). The snapshots I included previously come from ChipScope.

What I meant with the training patterns is that they should be aligned after a SYNC pulse, actually that is -I guess- their purpose,  but they are not; and obviously when you change from TEST to Normal mode the sinusoidal signals are not aligned either. 

a. I understand then that you have not tried the calibration package in four channel mode?
b. have you seen the training patterns aligned after a SYNC pulse in one (or four) channel mode, in either the reference design or the calibration package?

c. It is still not clear to me whether I have to provide that SYNC pulse as described in E2V app. note? We need to be clear on this as we are making the PCB suggested in that app. note in order to provide the correct SYNC pulse, but maybe this is not needed with your calibration package?

d. Do we have to perform the calibration of the ADC every time the it is turned on?

Thanks,
Daniel






Hallo Daniel,


How do you collect samples? Our reference design is grabbing samples from one channel at a time, so the snapshots from each channel do not align in time. Synchronization is not only about the E2V chipset, its also about the FPGA implementation.


Our calibration package ensures that samples collected from the four channels are in sync. In the calibration package this is done for one channel mode (90 degree phase difference between the channels). I guess changing the E2V chipset mode from one channel mode to 2 channel mode will result in the desired mode with 4 channels exactly in phase.


The training pattern in the E2V chipset is, as far as I know and have experienced, not reset upon a sync pulse.


Best Regards,
Peter
Hi Peter!,

Thanks for your reply.
We are not using the ADC at 5GSps yet, but in 4 channel mode at 1.25 Gsps each.

By SYNCHRONIZED I mean that if I send the same sinusoidal signal to the 4 channels at the same time I would expect that the resulting samples for each channel overlap (or maintain a minimum delay smaller than 1 sample period). A pulse in the SYNC input on the ADC chip should do it.
As you see in the figure 3 attached, this is not the case, the samples maintain a relative latency of some samples (not just a delay smaller than a sample period); this latency is not deterministic, every time I program the FMC125 we got different values, sometimes  2, 3 or even the 4 sampled channels coincide and sometimes not.  I have used both, the SYNC from CPLD as in your C reference design and a external pulse. Have you observed this before?

In the same figure you can also see the samples in TEST mode "ramp" after a SYNC pulse, only 2 of them are aligned. (The TEST mode "flash" is not relevant as e2v told me that they have an issue with it)

The question is then, does the calibration package guarantee that,  in this scenario (4 channel mode @1.25Gsps each), the samples of each channel will be aligned i.e. synchronized?

If so, do you (or we) have to send this SYNC pulse as explained in e2v App. Note 1083B (fig. 4.)?

Thanks, I am already in contact with the sales team.

Daniel

Hello,


We have successfully implemented 5GHz sampling mode using 4 channels in parallel, synchronized and calibrated. The complete package comes with a reference design (firmware and software). I can ask our sales team to contact you if you're interested. Please let me know.


Were told by E2V that you can give as many SYNC pulses as you want; once sync'd it will not loose sync. However this approach only works for synchronizing the channels on one card. We have not synchronized multiple FMC125, but we have done it for similar designs using our FMC408; Clock and trigger distribution FMC. It required tuning the clock/sync relationship to achieve synchronization.


[quote]Could you tell me which components are these?[/quote]
Buffer: NB6N11S
Mux: SY89547L


[quote]Or the total delay from the SSMC connector to the e2V chip for both the CLK and the SYNC inputs?[/quote]
This information is not available.


[quote]There are different ways to terminate a LVPECL signal either using both or just one of the I/O differential pair, usually providing a reference voltage, therefore we need more details about placement of extra components to be LVPECL compatible or should we send the boards back to you?[/quote]
If the default build does not work for you we can define a customization that need to be carried out by 4DSP to maintain warranty on the product.


[quote]Moreover I guess that the 1:2 buffer already has internal 50 ohm resistors?[/quote]
Please refer to the NB6N11S datasheet. The board design allows for termination of the Vtd pins.


Best Regards,
Peter