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FMC125 few issues

Good morning everyone,


w[font=tahoma][size=13px]e bought FMC125 mezzanine card and I am trying to work with it. I have few questions. I will be glad if you can answer on them:[/size][/font]

[size=1em]1. We need to lock sampling clock on ADC to some multiple of 40.08 MHz (as high as possible). As I understand from a manual I should set some bits in 1st register: (MSB-LSB) 0000_1110 (0x0e). (0, Normal_operation, Normal_operation, sync_from_FPGA, internal_clk/reference). Am I right? Information if is it possible (and how) to lock sampling clock with our frequency is [/size][size=13px]crucial[/size][size=1em] to develop project with your card.[/size][size=1em]2. I use "non-standard" carrier compatible with ANSI/VITA 57.1 standard.[/size]

[size=1em]2. There is Virtex6 FPGA on board. As I know I cannot use directly your StellarIP software to design my project. I have three sub-questions:[/size]

[size=1em]- why in temperature registers and analog registers are 0 values instead of some temperature and voltage values? Should I initiate such measurement? If so, how can I do it?[/size]

[size=1em]- how can I read/write to CPLD registers? I can see in bridge i2c-SPI data sheet that I need to send i2c frame like this: Start, [/size][size=1em]Addres(7bits), W/R(1bit), Ack(1bit), FunctionID(8bit = 0x08 [/size][size=1em][font=Verdana]- CPLD choosen), Ack(1bit), Data(0-200bits), Stop. How that "Data" should look like to read from Register X (X = 1, 2, 3)? How does bridge know to ask for X register in CPLD? (That is CPLD is obvious - via Function ID). It is not given in manual.[/font][/size]
[size=1em][/size]
[size=1em][font=Verdana]- when I scan i2c addresses on my empty carrier I got reply from 6 devices on carrier:[/font][/size][size=1em][font=Verdana]addresses: 0x1A, 0x2A, 0x4E, 0x56, 0x7A, 0x7E[/font][/size][size=1em][font=Verdana]when I plug FMC-ADC card on my carrier I expected 3 more addresses (temperature, EEPROM, bridge), but I got:[/font][/size][size=1em][font=Verdana]addresses: [/font][/size][size=1em][font=Verdana]0x1A, 0x2A, 0x4E, 0x56, 0x7A, 0x7E and "new ones": 0x28(bridge), 0x48(temp), 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, x057. That set of 0x5X addresses covers my carrier 0x56 address and the reason why it looks like this is unknown. Probably not because of my carrier. Do you have other i2c devices on FMC-ADC?[/font][/size]


[size=1em]Thank you for reply in advance.[/size]
[size=1em]Kind regards,[/size]
[size=1em]Piotr[/size]

Dear Sir,


1. The sync mode is suited to lock the 4 ADC core to the same clock. I assume you are trying to use internal sampling clock locked to a 40.08 (multiple) external reference. You should use 'CLKSRC' set to '011'. 'SYNCSRC' should indeed be set to '01'. The sync pulse should be sent as soon the clocks are stable and allow the 4 ADC core in the chip to be in sync as per the clock. You will need to also configure the clock tree chip, AD9517 to use the external reference.


2. The fact you cannot use StellarIP should not prevent you to gain some knowledge on the reference design. There will be too many questions if you decide to start everything from scratch, this is a complex product. I would really recommend not to jump over the usage of reference firmware/software on a supported carrier. The firmware has an i2c master star in charge of i2c communication, check Fmc12xAPP\Libs\I2CMASTER\Impls\i2cmaster_fmc12x.cpp, function i2cmaster_getdiagnosticsFMC12x(). Every call to sipif_readsipreg() reads from a chip register. The firmware maps all the chip to a given address. If you look at this function you will see that writing to configuration registers is required in order to get anything out of the chip. fmc12x_cpld.cpp typically communicate with the CPLD though the firmware also.


The i2c addresses thing is due to the fact our EEPROM device discard some of the address bits, the device will answer to several addresses. If you get address conflict, then the i2c chip on the FMC125 should be changed or removed, this should be carried on by 4DSP in order to keep your warranty.


The step I will be taking for these steps would be:


- Procure myself KC705, VC707 or ML605, run the default reference design, experiment with the external reference, etc.. I would be paying special attention to the software as the software is actually configuring the whole chipset, the firmware simply maps chip to a given address.
- Take the same firmware ( StellarIP only generates a full ISE project ) and change the UCF file to match your carrier physical constraints. If you don't have Ethernet, then the mac engine star should be replaced by a state machine sending all configuration read/writes. Same in this case, the software have all the addresses and the values but we don't have a configuration table.


- Answering questions by looking at the firmware CD (Constellation documentation) and SDs (Star documentation) as well as the source code, helping myself with simulation if required.


I hope that helps,
Arnaud

Hi Arnaud,


thank you for your advice.


ad 1. You are right, 40.08 MHz will be my external reference. Register should be set as you mentioned.


ad2. I borrowed ML605 and I can download bitstream using iMPACT (given as a recovery .bit and also synthesized one in ISE from StellarIP example project). When communication will be OK, I will transfer that part of a project into my carrier design project. But in this point I cannot communicate with ML605 using software. I got common error ffffffff. I followed FAQs and that thread [font=verdana][size=78%][url=http://www.4dsp.com/forum/index.php?topic=1058.0]http://www.4dsp.com/forum/index.php?topic=1058.0[/url][/size][/font] . Firewalls are off, jumpers in proper positions, direct connection PC-Board via short Ethernet cable, 4DSP network driver is visible, FMC in proper slot. Only thing that: "[font=verdana][size=78%]If the top center LED near the Ethernet port is lit on the ML605 then the link is up at 100Mbps which means the firmware loaded fine and the Ethernet was properly reset." [/size][/font][font=verdana][size=1em]LED does not light. [/size][/font][size=78%]


PS. At the moment i2c conflict on adresses 0x50-0x57 is not a problem.


One more thank you for your answer.


[font=Verdana]Kind regards,[/font][font=Verdana]Piotr[/font][/size]
Dear Sir,


One step forward, and two steps back. This common error indicates an issue of communication, one read to address 0x2000 in the constellation space is failing. Do you have any LED on on the Ethernet LEDs on the ML605 lit? If they are all off, then the PHY is not up and running. Can it be that your IT environment have external firewalls? We have seen that with one of our customer. He would be turning off the windows firewall but there would still be 3rd party firewall running.


It could be a problem in which NDIS ID you are using, are you sure you are using the correct one? If you have a doubt, show me your enumeration list as well as the command argument you pass to the application.


Would you maybe have a machine not joined to your domain you have complete control over? It could be interesting to try both 100Mbps and 1000Mbps.


I will get one of our engineers to try this reference design (firmware and software) and see if that works for us.


I will keep you updated most likely Monday morning.


Best Regards,
Arnaud
Dear Arnaud,


LEDs nearby Ethernet port (2x3) are off. I turned off Windows firewall and anti-virus (contacted with my IT department).


I use Windows Command, go to example program and run it with parameters:
C:\Program Files (x86)\4dsp\FMC Board Support Package\Bins>Fmc12xAPP.exe 1 ML605 0 0 0


I will try to run any other example project on ML605 to see any LED lid or blinking. I will inform you if I have any Ethernet LED blinking, or lid. Also I will inform you in case of success in communication.


If I understand your correctly, in attachment is print screen with my NDIS's. I was trying with and without ticked IPv4.


Thank you for your reply.


Kind regards,
Piotr
Dear Sir,


When you run the application without argument you get a enumeration list. There will be list of supported Ethernet devices in your system. On a laptop you generally see one wifi adapter and one wire adapter. On standard computer you can have several wire adapter in the list.


Also pay special attention to the fact sometimes windows decide to re index NDIS adapters. This is argument number 3, after ML605. You place a '0' but you should find the right device in the list, which might be 0 or not.


The design does not use TCP/IP, it uses low level Ethernet packet manipulation.


Best Regards,
Arnaud
Dear Arnaud,


yes, I run that FCM12xAPP.exe without options. I can see only 1 position (given as 0. Network Card...etc, becouse on my computer there is only one card:) ). So I have not got so much choise to make a mistake in that point. When I put 1, I have error: "Problem opening the hardware, sorry...", what is obvious.


Yes, I know about that low level communication. So it is why I leave only 4DSP driver checked. I will try with any ML605 example program to run PHY and see any status on LEDs.


Kind regards,
Piotr
Dear Piotr,


A firmware colleague verified the reference design from the installer and he indicates it is working fine, can you send me a high resolution picture of your ML605 so I can verify jumper settings?. Is it possible for you to try on another machine?


Thanks,
Arnaud




Dear Arnaud,


here are a few photos of jumpers and switches.
I would like that:
- Ethernet cable given by Xilinx (straight, not crossover)
- Xilinx flash card not inserted
- no LEDs flashing/blinking/on nearby Ethernet connector.


Thank you.
Kind regards,
Piotr
Dear Arnaud,


FMC125 works with ML605!!! I have collected some data!  :D
At the moment I do not know what was the problem. I will investigate this and give you feedback.


Kind regards,
Piotr
Dear Piotr,


Thanks for the feedback, I put that a side then, keep me updated!


Thanks,
Arnaud
Dear Arnaud,


your project (firmware and software, communication between ML605 and PC) works when:
- flash card inserted
- J17 jumper between middle and top pins
- J18 jumper between middle and left pins
- J66 and J67 jumpers between middle and left pins
- J68 no jumper
- S1: 1000 (reading from left to right in normal board position)
- S2: 011010 (reading from left to right in normal board position)


Also I did some test (from default positions described above I changed only written switch/jumper):
1. FAIL: without flash memory card
2. FAIL: S1 in 0000 and S2 in 010100
3. PASS: S1 in 1000 and S2 in 010100
4. FAIL: without flash memory card and S1 in 1000 and S2 in 010100
5. FAIL: J66 and J67 between middle and right pins (I was trying with slower ethernet connection)
6. PASS: default board setting and Windows Firewall and Anti-Virus ON




I have one more question to you: when I run program: Fmc12x.exe 1 ML605 0 2 0
(ethernet, ML605 board, device index, Int clk and ext reference, vco type default) I get message: "PLL not locked!" and program goes into debug. I feed CL input from pulse generator as a square signal, 50 Ohm, frequency in range 10-100MHz (any, let say 40MHz). Do you know what is the reason?


Thank you!


Kind regards,
Piotr
Bonjour Piotr,


Thanks for the feedback. According to what I see I believe the ethernet PHY is not being init in the FMC125 firmware. It looks like it works when something contained on the flash card run before our firmware is loaded to FPGA.


About external reference, try to feed a 100MHz clock. This is what the reference design expects. This will be a starting point. Then you will need to look at the clock tree chip configuration to get it lock on a different reference clock.


Best Regards,
Arnaud
Bonjour Arnaud,


I did research both firmware and software. I think that I understand your product in details. It is piece of nice hardware :)


Meanwhile I was playing with firmware and ADC configuration. Now I need to run FMC with external clock.
- I feed CL input by 100MHz clock, from external generator, in software I set parameter "2" as internal clock, external reference. Sowtware works (PLL is locked)
- Then, for small changes in external reference (from 99.95 to 100.05MHz) PLL locks
- For others (like 90MHz) PLL does not lock
- For 100MHz and changes "A" parameter in clock tree - PLL locks
- For 100MHz and R or B changes - PLL does not lock
- I was trying to increase power of input clock (as it was suggested by Kyu in other posts on your forum) - PLL does not lock
- I followed registers in clock tree - I do not know which should I change to use external reference. In fact, As I understand schematics of your board, 100MHz oscillator and VCXO are very similar to external clock.


Can you give me a clue which registers should I set/change to work with different external clock (for example 10 MHz or 20MHz)? Should I change A, B, R and P parameters? (I do not think they are crucial for first run with external ref)


Thank you in advance!
Piotr
Dear Piotr,


Check Figure 7 and surrounding in the FMC12x user manual. All these settings are direct AD9517 register settings. The RF switches and the ref enable signals are also available.


I don't have the exact settings you need for the AD9517, sorry for that. Most likely AD9517 literature will get handy here.


Best Regards,
Arnaud