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FMC125 few issues

Good morning everyone,


w[font=tahoma][size=13px]e bought FMC125 mezzanine card and I am trying to work with it. I have few questions. I will be glad if you can answer on them:[/size][/font]

[size=1em]1. We need to lock sampling clock on ADC to some multiple of 40.08 MHz (as high as possible). As I understand from a manual I should set some bits in 1st register: (MSB-LSB) 0000_1110 (0x0e). (0, Normal_operation, Normal_operation, sync_from_FPGA, internal_clk/reference). Am I right? Information if is it possible (and how) to lock sampling clock with our frequency is [/size][size=13px]crucial[/size][size=1em] to develop project with your card.[/size][size=1em]2. I use "non-standard" carrier compatible with ANSI/VITA 57.1 standard.[/size]

[size=1em]2. There is Virtex6 FPGA on board. As I know I cannot use directly your StellarIP software to design my project. I have three sub-questions:[/size]

[size=1em]- why in temperature registers and analog registers are 0 values instead of some temperature and voltage values? Should I initiate such measurement? If so, how can I do it?[/size]

[size=1em]- how can I read/write to CPLD registers? I can see in bridge i2c-SPI data sheet that I need to send i2c frame like this: Start, [/size][size=1em]Addres(7bits), W/R(1bit), Ack(1bit), FunctionID(8bit = 0x08 [/size][size=1em][font=Verdana]- CPLD choosen), Ack(1bit), Data(0-200bits), Stop. How that "Data" should look like to read from Register X (X = 1, 2, 3)? How does bridge know to ask for X register in CPLD? (That is CPLD is obvious - via Function ID). It is not given in manual.[/font][/size]
[size=1em][/size]
[size=1em][font=Verdana]- when I scan i2c addresses on my empty carrier I got reply from 6 devices on carrier:[/font][/size][size=1em][font=Verdana]addresses: 0x1A, 0x2A, 0x4E, 0x56, 0x7A, 0x7E[/font][/size][size=1em][font=Verdana]when I plug FMC-ADC card on my carrier I expected 3 more addresses (temperature, EEPROM, bridge), but I got:[/font][/size][size=1em][font=Verdana]addresses: [/font][/size][size=1em][font=Verdana]0x1A, 0x2A, 0x4E, 0x56, 0x7A, 0x7E and "new ones": 0x28(bridge), 0x48(temp), 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, x057. That set of 0x5X addresses covers my carrier 0x56 address and the reason why it looks like this is unknown. Probably not because of my carrier. Do you have other i2c devices on FMC-ADC?[/font][/size]


[size=1em]Thank you for reply in advance.[/size]
[size=1em]Kind regards,[/size]
[size=1em]Piotr[/size]

1 person has this question

Dear Arnaud,


quick feedback. Finally I can use any external clock (even 40 MHz).
Main part of that external reference is clock tree and few registers responsible for R, P, A, and B values. Each of them is set in different register and has some constrains (written in clock tree, AD9517 datasheet). Main part of clock tree device is Phase Frequency Detector. It compares two numbers: fref/R and fclk/N. Those values need to be the same (or in some cases as close as possible). Then PLL is locked and we can use that sampling clock in ADC.


If I have more questions, I will write them in this topic in future.


Thank you,
Piotr
Good morning,


I have next piece of questions about analog input to FMC125. When I apply square pulse 1MHz, amplitude 300mV, output from pulse generator terminated 50 Ohms, signal applied via single-ended connection I have such effect like on a plot in attachment:
- "baseline" (ADC_1, ADC_2 and ADC_3 floating, not connected) is in the middle of ADC range ~128
- high pass filter behavior ([font=Verdana][size=78%]Of course effect is smaller with higher frequencies. )[/size][/font]


We measured analog input impedance and it is... infinity instead of 50 Ohms.
1. How should we couple our signals?
2. How is done single-ended input to differential in ADC? Could you show me part of schematic related to that analog part?
3. We would like to use single-ended input in full dynamic range.


Tank you for your reply in advance.


Kind regards,
Piotr
Dear Piotr,


I am not sure about the infinity, but I think the issue is simple here. You have an AC coupling card and you assume it to be DC coupled; There is a transformer on the input with a low frequency cut off of 3MHz.


The squarewave being "complete" on a spectrum point of view, what you see is the portion being discarded by the input transformers. Feed a sine wave far above 3MHz (the -3dB is at 3MHz) and see if that works.


There is a specific custom option where we directly connect the ADC input connectors to the e2v chip, I guess this is what you want to investigate around.


Best Regards,
Arnaud
Dear Arnaud,


you are right, when I feed input by sine more than 3 MHz (in fact lower frequencies are also acceptable), I get nice recorded set of data. But what I am mostly interested in is not having "orange" effect visible on attached plot - going to baseline. (signal is burst of pulses with defined leading and trailing edges, amplitude 150mVpp).


In fact we are interested in that custom option you mentioned. Can you recommend me what should be changed on board or do you prefer to do such modification in your company?


Thank you.


Best regards,
Piotr
Hello Piotr,


It depends if you are willing to lose your warranty or not. Any kind of soldering is prohibited. I think it is safer to send the board over so it is properly modified and tested, this is important also.


You should get in touch with saleseurope@4dsp.com to discuss pricing and lead time for the modification.


I will close this topic if this is fine with you, feel free to open another one for next inquiries!


Best Regards,
Arnaud
Hello Arnaud,


I would like to thank you for any help in this topic.


You can close that thread.


Merci beaucoup!


Best regards,
Piotr
Hello Piotr,


Always glad to assist one way or another :)


Thanks,
Arnaud