I'm trying to use the VC707 with an FMC126 and was looking at the I2C control section in "fmc126_if.vhd" and unless I'm mistaken, it does not look like it is properly connected.
Between lines 685 to 703 (see below excerpt), the top-level pins i2c_scl and i2c_sda are connected to IOBUFs but the O inputs of the IOBUFs are not connected to what I would expect. I would expect the O input on iobuf_scl to be connected to and_reduce(scl_o) and the O input on iobuf_sda to be connected to and_reduce(sda_o). Instead, they are connected to scl_i and sda_i, respectively, which appear to not be assigned anywhere else.
Am I missing something? Do I have the most recent version of the code?
oe_scl <= and_reduce(scl_oe);
iobuf_scl : iobuf port map ( I => '0', O => scl_i, IO => i2c_scl, T => oe_scl );
oe_sda <= and_reduce(sda_oe);
iobuf_sda : iobuf port map ( I => '0', O => sda_i, IO => i2c_sda, T => oe_sda );
It's a tri-state buffer. On the hardware, I2C lines are pulled up, which means I2C lines are high as default and become zero whenever output enable (oe_scl/oe_sda) is activated. "scl_i" and "sda_i" should be connected to "fmc126_i2c_master" and "fmc126_sc18is602b_ctrl" blocks. Are you sure they are not assigned to anywhere?
about 3 years ago
Thanks for your reply, Kyu.
I think I was misunderstanding how the BUFIO works in the FPGA. Since there is a pull-up resistor connected to the "IO" port of the IOBUF and the input of the IOBUF ("I" port) is tied low '0', connecting the outgoing scl_en and sda_en to the "T" port of the IOBUF effectively results in the output going low for T = '0', and high for T = '1'.