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FMC126 issues (on ML605)

Hello everyone!

We have 2 problems with FMC126 ADC's:

- A few minutes ago, one of the ADC's just stopped working. When we try to access it via Fmc12xApp.exe, we get the following error message: "Could not initialize FMC12x.CPLD, Could not initialize FMC12x, exiting". It seems that the ADC is not responsive at all. Proper cooling was given all the time. What shall we do with it?

- When connecting the same signal to multiple inputs, we get a phase difference between the connectors (all ADC's are software triggered at the same point in time). In particular, the phase difference is approx. 5.7 degrees between ADC A and B and 17 degrees between ADC A and C (signal is a 20MHz sine wave). The results are reproducible for multiple measurements and there is no difference in cable lengths for the different connections. What could be going wrong?

With best regards,
Philip

Hello Philip,
For the first issue, we can try to reprogram the CPLD if that does not work the card might need to come back with RMA. Can you provide me with the hardware revision of your FMC12x PCB, you can see that on the silk screen. Can you also provide me with a FMC serial number.
For the second issue, there is a sync pulse requirement as well as analog compensation for phase, offset and gain required. The reference design does not take care about that.
Best Regards,
Arnaud
Hey Arnaud,

Thanks for your response. The S/N of the malfunctioning ADC is 1938 and it is hw rev 2.

For the rest, I will take a closer look at the calibration methods you've mentioned.

With best regards,
Philip
Dear Philip,


Please find attached a .jed for reprogramming your CPLD, I've sent you the password per email ( as this is a public area ).


Let me know if that helps or not!


Best Regards,
Arnaud
Hey Arnaud,

Thanks for the JED file, will test it right away.

I have looked into the triggering of sync pulses for the AD (the phase calibration on the AD itself covers ranges of +-15ps, that is a magnitude smaller than the phase differences I observe during my measurements). Unfortunately, documentation (SD039) says that setting of the sync bit in ADC PHY command reg is not supported on ML605. Can you tell me why this is the case? I've looked into the VHDL code of the extracted design and all connections, as well as the mapping in the corresponding UCF file, seem to be correct. I've tried to apply the sync pulse nevertheless by modifying the Fmc12x software, but still get delays ranging between 1.2ns and 12ns for a 20MHz input signal (modified the code as well to have a single sw trigger for all channels, get similar delays for 2 channel mode and common mode).

Besides, I observed that there are some slight clock differences between the different ADC's, at least the test application says so. Could this be part of the problem? Here is part of its output (I've disabled channel C and D):

ADC A PHY Clock  : 156.25 MHz (Fs = 1250.00)
ADC B PHY Clock  : 156.23 MHz (Fs = 1249.88)
ADC C PHY Clock  :  0.02 MHz (Fs =    0.12)
ADC D PHY Clock  :  0.02 MHz (Fs =    0.12)

With best regards,
Philip
Hello Philip,


There was a sync bug on silicon revision 1.0 which required to actually send 100 sync pulse to be sure to have one valid, this could be a reason.


Did you also modify the FMC12x internal FIFOs to keep data? Because in the default firmware, FIFO not actively connected to an output (via the router) will loose its data, in other words, data from the three FIFOs unconnected goes in a black-hole. This will end up having temporal difference between the channels, surely.


Note that we have successfully implemented a 5Gsps design which implicitly means it is possible to have the channels in sync for both analog and digital domain. This is an extra package we are selling for FMC126, it includes a modified reference firmware (synchronous) as well as a software able to find compensation values. The same software takes snapshots at the end, reconstruct the 5Gsps buffer and calculate post FFT analysis. The whole package is delivered with source code.


I hope that helps,
Arnaud

Hey Arnaud,

First of all, thanks for the JED file, that did the trick -> ADC is working again.

Concerning the sync problem, I will try to test it with multiple sync pulses, but afaik I have hardware rev 2, so the problem should not appear here, right?

I have also modified the sw to keep the fifos until I release them 1 by 1.

Thanks again for your help!
Hello Philip,
I guess your modification are not completely correct then.
I would not expect the sync bug to be in rev2, but we never know.
Best Regards,
Arnaud
Hey Arnaud,

Could it be that the delay I am experiencing is caused by the fact that the sw trigger enables all FIFOs at the same point in time, whereas data sent from the ADCs to the FIFOs has different delays (or the other way round)? The more I look into it, the more I get the feeling that it has nothing to do with syncing and as I said before, the phase correction that can be applied via calibrating the ADCs themselves is a magnitude smaller than the delay I actually have.

With best regards,
Philip
Further information:

I perform the operations as follows:
- Disable offloading of all FIFOs
- Enable all ADC channels
- Arm DAC
- Send SW trigger
Repeat for all channels x:
  - Configure router for channel x
  - Enable offloading for FIFO x
  - Read data

The IDELAYS that are calculated by the software are the following (channel C and D disabled, large delay is between A and B):
[font=courier]IDELAY Ch 0: 20 | 19 | 18 | 19 | 20 | 18 | 18 | 19 | 15 | 16 |  0
IDELAY Ch 1: 10 | 11 | 11 | 10 | 10 | 11 | 11 | 11 | 11 | 11 |  0
IDELAY Ch 2:  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0
IDELAY Ch 3:  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0[/font]
Hello,
I am not sure. Have you tried to simulate the design? The problem here is this is not covered by a standard technical support and we are selling a design which looks like what you are trying to achieve.
If you need extra support you could also purchase and extended technical support contract.
I am attaching user manual of our 5/2.5Gsps package.
Best Regards,
Arnaud
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