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Problem when doing 4FM getting started guide

Hello


I followed the steps in the section relative to zedboard in the strated guide is page 65. I open the ISE command prompt but when i do go 325_zedb_fmc150.bit, i get some erros.


Error Executing User Script: download_elf.tcl
Error :: ERROR: Cannot write to target


Failed to lock the JTAG cable for exclusive access


I already tried to release cables but the samething occurs.


What am i doing wrong?




This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.
Hello


[font=Verdana]About the hanging PHY negotiation, i removed the line that you have said and now it is working. Then i tried to work with FMC analyzer, it didn't work, but then i searched here and i found a post saying that it doesn't work with zedboard.[/font]

[font=verdana, arial, helvetica, sans-serif]Now, i'm reading all the documents provided and i'm trying to understand how should i start my project.[/font]

[font=verdana, arial, helvetica, sans-serif]Thank you for all the help[/font]

[font=verdana, arial, helvetica, sans-serif]Joao[/font]
Dear Joao,


Was the information sufficient, have you been able to move forward?


Best Regards,
Arnaud
Joao,


I will point you to the 4FM Getting Started Guide, it describes the firmware, where is the source code and many other things about StellarIP. Check for the CD and SD documents in the firmware source code. Look at the doxygen documentation in the software, etc.. As you understood you are dealing with complex code and complex design you will need to push a lot of efforts getting everything right, but this is a normal integration task.


How to change a source code? I am using notepad... If you mean how to recompile it? With Xilinx tools for the firmware and Visual Studio for the software.


So many people took these steps before you, if you want 4DSP to guide you step by step, please contact saleseurope@4dsp.com and arrange them an extended support contract.


Thanks,
Arnaud



Thanks a lot i'll try what you said and i'll post news.


About the reference design what specific documents should I read to understand all the information? And where is the source code and how should I change it then?


Sorry for my questions but I want to do the things correctly.



Dear Sir,


As far as the Xilinx error is concerned "Failed to lock the JTAG cable..." you will need to ask Xilinx about that. This is about your Xilinx tools not communicating well with your Zedboard. Unfortunately I cannot do anything about that.


About the hanging PHY negotiation, this could be related to a problem in recent Xilinx tools, you should remove the line with rst text in the download_elf.tcl and see if that helps.


For you own design, well, you have a a reference design delivered as source code, you will need to start by understanding this design and then you will be able to modify it as per your requirement, only a normal integration task.


Best Regards,
Arnaud
I'm here to update. After some tries i can pass that problem and the download_elf.tcl is downloaded successfuly. In the terminal of Teraterm  i get the message that should appear until Waiting for PHY to complete negotiation, then it holds there and doesn't show the message " autonegotiation complete".


I don't know what is happening and i'm becoming a litle confused with this, and i'm not near close of what i have to do. :-\




It is supposed to put the FMC150 card working receiving a 50MHZ sinewave from a signal generator and then bypass that input to output and see if the result is the same. That project should work with zedboard and FMC150.


What path should i take to start implementing this project? I know that probably i have to make everything from the start, but my problem isn't doing, the problem is that i'm not understanding how should i start.


Can anyone give me some guidelines or some information to how should i proceed?


Thank you in advance