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Regarding AUXIN P/N (U9P/N)

[size=2]I want to use the 200-MHz clock (differential) coming from ML605 to drive DACs of FMC150 via U9P/N of CDCE72010.[/size]
[size=2]Can anybody tell me an example of the coe file for initialization of ROM for [font=Verdana]CDCE72010?[/font][/size]

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Thank you for your help.
I got enough information about this.
Dear Sir,


Is there anything I can do before to close this topic?


Best Regards,
Arnaud
Dear Sir,


The way we do it is to use the SMA connector on the Xilinx board to generate a clock and a trigger and we use that as clock source for elementary tests.


The reference design has a software trigger mechanism, look at the main.cpp, by writing to a FPGA register, the software is able to trigger the system.


Best Regards,
Arnaud
Thank you for your reply.
I want to use the 200-MHz clock of ML605 to trigger the DACs of FMC150.
Does this mean that I have to let the 200-MHz clock come out from a GPIO of ML605 and connect to the "CLK" port of FMC150?
Is there any method to trigger the DACs via LPC?
Dear Sir,


We do not have out of the shelve ROM init files for all the possible use case. What we do provide to customer however is a reference design (firmware and software) able to completely configure the FMC150 for both internal and external clock mode. The firmware and the software are both documented.


You will need to check check CDCE72010 datasheet and the FMC150 user manual in order to understand how to configure the CDCE72010.


I hope that helps.


Best Regards,
Arnaud