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Extracting ADC output in VHDL from reference design

Hi,

We are trying to generate a 500 Hz square wave from the DAC, and integrate over part of the response from a circuit. The generation seems to work seamlessly. The integration should be done over 50K samples from the ADC, 0.1 ms after the positive edge, for each period of the generated signal.

We want to modify the reference design VHDL. There are two questions:

1. Which signal(s) should we extract from the given design to get the ADC outputs?
2. What tap delay should we use, and how should we insert it directly in the VHDL logic?

Thanks!

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.
Dear Sir,

We will be closing this topic next Monday due to the topic inactivity!

Best Regards,
Arnaud
Hi,

Please note that I am not really suppose to help you with custom designs unless it is a simple straight forward question.

I don't quite understand your questions. What reference design are you using (what carrier board do you have)?

Correct me if I am wrong but what you are trying to do is generate a 500 Hz square wave in the DAC that goes into some circuit and the output of that circuit goes into the ADC. You want to capture 50K samples from the ADC (and add the samples?) .1 ms after the positive edge of each square wave coming out of the DAC.



1. Which signal(s) should we extract from the given design to get the ADC outputs?

Do you mean how do you get the ADC outputs? You probably want to use the external trigger (see the FMC150 User Manual) which begins the capturing process on the rising edge of a signal. You will have to modify the the vhdl code so this trigger is delayed by the amount you want.



2. What tap delay should we use, and how should we insert it directly in the VHDL logic?

Which tap delay are you referring to? The capture trigger for the ADC?



Regards,
Luis