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Sending a digital signal through the FMC151

Hi,
I have an ML605 fpga board and have the FMC151 attached on the lpc fmc.


According to the spec, to send a signal through the DAC, I need to send an LVDS clock signal, LVDS data, and LVDS frame signal, as well as the control. I know how to control clock, frame, and data transmission easily, and understand that. But I'm not sure which parts of the control I need to manage to enable the data transfer.


According to the spec of the DAC3283, the control takes in an SD_enable and SClk and a txenable. How can I configure the control to send my signal through? I'm a little lost here and the VHDL getting started reference design was a little too all encompassing for my needs. I just need to configure the control to allow me to send my 8 bit differential pair signal through.


Thanks
-Erik

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.
Hey paul,


So yeah with the Stellar IP generated ISE project and VHDL code, I ran the FMC15xAPP for the 0-31 and noticed that at delays 0, 1, 2, 3, 8, and 11 that I got a normal wave. So in order to tailor the board to my purposes I think I will be working with this VHDL code. Timing delay issues will probably rise up again but hopefully it's not too bad.


Also, that sounds great. Likewise, if you run into any problems, you can contact me at emeade@imra.com, because I might have previously encountered the same problem.
[size=2]Hello Eric,[/size]

[size=2]Good to hear from you. [/size]

[size=2]As far as I understand, the tap_delay of 26 [b]will only work[/b] for their bitstream located in the following directory. [/size]

[size=2][b][i]C:\Program Files (x86)\4dsp\Common\Firmware\Recovery\418_ml605_fmc151[/i][/b][/size]

[size=2]If you create an ISE project from  Steller IP and create a bit-stream, this tap_delay may not work. If you create your custom IP to this design, firstly you should make sure that the design meets the timing requirements. [/size]

[size=2]I was provided with an exe file that would generate tap_delay of 0 to 31 and generate text files when you run FMC150xAPP (attached in the post)[font=Verdana]. I also created a[/font][font=Verdana] matlab[/font] file which accepts a tap_[font=Verdana]delay and plot's the graph corresponding to tap delay using [/font][font=Verdana]Matlab([/font][font=Verdana]attached in post). [/font][/size]

[size=2][font=verdana, arial, helvetica, sans-serif]My plan is to generate text files for all tap_delay, plot these text files in Matlab and select a tap_delay which gives decent results. Then adding this tap_delay in the visual studio, you could Build-Generate-Run a new FMC150xAPP application. [/font][/size][font=Verdana][size=small]Technically, this should fix the issue related to synchronization.  [/size][/font]
[/size][size=small]
[font=verdana, arial, helvetica, sans-serif][/size][size=2]4DSP do not do any kind of support for custom design unless a support contract is purchased. So, I feel that it would be great if we could help each other and solve problem related to our custom design. [/size][size=small][/font][font=Verdana][/size][size=small]Please feel free to contact me through email at paulleons@gmail.com if you need anything. [/size][/font]

[font=verdana, arial, helvetica, sans-serif][/size][size=2]regards,[/size][size=small][/font]
[font=verdana, arial, helvetica, sans-serif][/size][size=2]Paul Leons[/size][size=small][/font]
[/size][size=2][font=verdana, arial, helvetica, sans-serif] [/font][/size][size=small]
Hey paul, have you gotten the reference design to work by adjusting the CLK_IDELAY to 26 or 27?


For me, using the fmc15xapp produces good sine waves, however using the reference design I have yet to find a valid CLK_IDELAY value, if you've found one, let me know. :)
Paul that is true.

What you are running is a reference design for the FMC151 made to run on many different carrier boards. Different carrier boards will have variations in trace lengths and termination schemes etc., so there is a calibration step that is required to interface to the ADC.

If you are rebuilding the firmware you might also need to re-calibrate if the interface is changing, you can use a PLL or BUG or BUFR and they get placed in different locations etc, so different delays can result from changes in firmware as well.

Ideally there would be an automatic calibration sequence before sampling begins, which we have in other reference designs. Unfortunately for the FMC151 reference design this is done manually in software at the moment.

Hello Eric,


I use the same board as yours (FMC 151) and I have the same problem as yours. If a tap_delay of 26 is given, I get a much better sine wave.  I wonder if this was a mistake in board design itself as we have the same problem with the same fix to the problem.


4DSP has agreed to have long term fix to this problem, but I am skeptical on how they are going to fix it.


For now, the tap_delay of 26 works for the reference design, but once, we do make changes to reference design (add custom IP's etc) , then the tap_delay of 26 may not work.




Paul
Success!

Here are my results for both 26 and 27.

It's nice to have figured this out.

The serial number appears to be KDJV 000024.

Hi Erik,

There is someone having the same issue as you here:

http://www.4dsp.nl/forum/index.php/topic,2922.msg15758.html#msg15758

For him a delay of 26 works.  Download and try the [url=http://www.4dsp.nl/forum/index.php?action=dlattach;topic=2922.0;attach=3223]Fmc15xAPP_Search_Tapiod_clk.rar[/url] linked in that post. It will try all taps and save them to a text file then you can see which is a good range. An automatically calibration will be available in the near future.



Regards,
Luis
From your console it looks like everything as far as firmware / software is correct.  What is the serial number of your FMC151, I can look up the test records of your board before it was shipped out. Also seeing ADC1 would be useful information just to make sure it is behaving the same.

The most likely cause of the problem we are seeing is that the clock and data are not being aligned correctly.  Like I said I can reproduce your problem my adding delay on the clock. You've tried delays of 7, 14, and 21. Can you try a few more and see if you get any better results.


tapiod_clk = 0x03; tapiod_data = 0x00;
tapiod_clk = 0x0A; tapiod_data = 0x00;
tapiod_clk = 0x0F; tapiod_data = 0x00;
tapiod_clk = 0x12; tapiod_data = 0x00;
tapiod_clk = 0x19; tapiod_data = 0x00;
tapiod_clk = 0x1e; tapiod_data = 0x00;

This should pretty much cover the range.


Sure thing!

So the ML605 board I have is revision D. Also, just to check one more time, the .bit file is supposed to be this one: C:\Program Files (x86)\4dsp\Common\Firmware\Recovery\418_ml605_fmc151\ml605_fmc151.bit right? Mine has a size of 4544 kb, just to further verify.

I only have the adc0 hooked up currently, but since both channels go to the same texas instruments adc, it shouldn't be an issue, if you really want me to hook up both to a dac, I can.

Attached is the clk 07 and data 05 results. Along with the program output.

Also, I'd like to say a big thank you to you guys for helping me troubleshoot this.




Hi Erik,

I want to confirm a few things. What revision of the ML605 do you have? I have an ML605 + FMC151 with me so I tried a few tests for you, attached are my results.

ml605_fmc151.txt - Your console output should pretty much look exactly the same

fmc151_clock0.png - default settings for tapiod_clk, loooks good to me

fmc151_clock7.png - I set tapiod_clk = 0x7, now my signal is distorted


My distorted signal looks similar to yours. My guess is you have a different revision of the ML605 than me and the IODELAY must need to be adjusted.


Can you go into fmc15x_adc.cpp and at line 140 add the following:

[code]
        if(rc!=SIPIF_ERR_OK)
            return rc;
        Sleep(10);
        rc = sipif_writesipreg(bar_adc_phy+0, 0x08);
        if(rc!=SIPIF_ERR_OK)
            return rc;
        Sleep(10);
    }

printf("%x \n", tapiod_clk);    ////////////////// // ADD THIS
printf("%x \n", tapiod_data);  ///////////////// // ADD THIS

    /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
    // ADC SPI Test, read back one of the programmed registers to see programming was succesfull
    rc = fmc15x_adc_readreg(bar_adc, 0x50, &dword);
[/code]


Now try changing the tap values to

tapiod_clk = 0x07; tapiod_data = 0x05;

Can you attach your your console output and both your adc0.txt and adc1.txt. This will allow me to confirm your software build and firmware is working correctly.

If that all works then I think it is a matter of adjusting tapiod_clk to the correct delay.


Regards,
Luis

Thanks, I downloaded that and compiled with no problems, however, still no cigar. Graphs look pretty similar but I'll attach them anyway.

I'm out of attachments for the last 2 variations, but they look pretty much the same, anything else I can try?
We use Visual Studio Express 2012, which is free.  But it should work with any c++ compiler you just need to set your build paths to have:

C:\Program Files (x86)\4dsp\4FM Core Development Kit\Incs
C:\Program Files (x86)\4dsp\4FM Core Development Kit\Libs
Do I need to have visual studio to recompile the main.cpp?
Hi Erik,

That might be a problem with the settings of the IODELAY tap values for FPGA on the pins where the ADC data and clock are coming in. This could happen for example if you have a different revision of the ML605 than was used in making the software (because the routing could be different).


If you look in main.cpp those settings are set on line 386



[code]
    // Default number of cards is 1 per board - exception is for PC720 which could have two
    numFmcCards = 1;
    odelay_tap = 0;
    switch (constellation_id)
    {
    case CONSTELLATION_ID_ML605:
    case CONSTELLATION_ID_FMC151_ML605:
        printf("Found ML605 hardware\n\n");
        tapiod_clk = 0x00; tapiod_data = 0x00; /// T
        break;
[/code]


Can you try changing the line 386 to some of the each of the settings below and let me know if you see any improvements in samples the ADC is sending to the FPGA.

// try adjusting clock tap
tapiod_clk = 0x07; tapiod_data = 0x00;

tapiod_clk = 0x14; tapiod_data = 0x00;

tapiod_clk = 0x21; tapiod_data = 0x00;

// try adjusting data tap
tapiod_clk = 0x00; tapiod_data = 0x07;

tapiod_clk = 0x00; tapiod_data = 0x14;

tapiod_clk = 0x00; tapiod_data = 0x21;

Regards,
Luis