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Getting started with FMC 151 in ML605 board


I would like to get some technical support to get started with the FMC board.


My project involves an EDK design with microblaze processor and some IP's which performs certain functions. I would like to know how I can interface my EDK design with the interface IP's provided by the 4DSP.

The reference design to add an "AXI4-Streaming to StellarIP Interface" for Kintex 7 seems to be a very complicated design. 

Is there any reference design(ML605) for reading/writing values into the interface IP from microblaze for generating and analyzing data from the FMC board?


regards,
Paul

Dear Paul,


The AXI-Streaming FIFO is a reasonable tutorial in term of complexity.


We do not have other reference designs unfortunately. The way this could be implemented is creating an EDK peripheral translating Axi bus transactions into StellarIP command wormhole transactions. You would map this peripheral into your XPS system and you could then access the StellarIP addresses from your Axi address space.


This looks like a simple task but there are quite a few pitfalls. As these steps are not covered by standard technical support (integration issues) you might want to ask sales@4dsp.com about a microblaze reference design. We do not have one handy but could implement one for you.


Best Regards,
Arnaud
Thank you very much for the reply.


In my opinion as a customer who is familiarizing with Steller IP, a reference design should be as simple as possible, eg: generating a sine wave/square wave etc. Another reference design could be provided to do the ADC conversion and viewing the graph in chipscope. [b]AXI4-Streaming to StellarIP Interface [/b]tutorial involves lot of IP creation, port mapping of lot of signals in VHDL. The tutorial had lots of mistakes as well.


A reference design provided by Avnet is much simpler : Generating a impulse signal which is fed back to an FIR filter via an ADC which compares the received data with a golden model from matlab. But the project is made for kintex 7 in planahead and once project settings are changed to ml605, the tool gives lots of error in the implementation (as there is a mis-match in  the UCF and IP cores).


As you said, integrating Steller ips to XPS is not very straight-forward. Hence, I would request a reference design to interface required IP's with a microblaze based design.


regards,
Paul

Dear Paul,


The simplest example is the 400_trainmat which is covered by the 4FM Getting Started Guide. It is actually the basics of adding a custom star in a design. You can wrap anything as star, this could be a system.vhd wrapper and the xps netlist.


You can probably ask for a custom reference design meeting your expectation, please contact sales@4dsp.com is this is a path you want to take.


Best Regards,
Arnaud
This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.