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Noise with FMC151

Hello,


I am trying the reference design provided with ML605 and FMC 151. I am generating a 5MHz sine wave with an amplitude of 1V. I am communicating with the board with Ethernet.  I am using the following cable to connect the FMC 151 (MMCX) with a signal generator : http://www.pasternack.com/mmcx-plug-bnc-female-rg174au-cable-assembly-pe36738-48-p.aspx


The waveform obtained with noise is attached with this post. I was wondering if the board would have so much noise in the waveform. I also noticed that the board is becoming much warmer IC. Is this normal?


regards,
Paul




This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.
Paul,


I would double check the chipscope sampling clock then.


The fact you get proper data saved to file indicate the reference design is working. Modification on the reference firmware are not supported unless you have a extended technical support contract in place.


Because you indicate you have the proper data saved to file indicate the initial issue is resolved and therefor I am closing this topic.


Best Regards,
Arnaud



Thanks for the reply.


But I have some more concerns regarding the tap-delay.  I have my own custom Ip which connects to two signals, namely phy_out_data0 and phy_out_data1 (from the reference design) and I observe these values in chipscope.


The was implemented and had met timing. Now, a tap-delay of 0 was observed to be ideal as I got a sine wave similar to untitled.jpg.


However, when I see the same waveform in chipscope, the sine wave seems to be distorted as in image_0.jpg and image_1.jpg.


Is there a possible explanation for this behavior?


Paul
Paul,

it does not matter what frequency you use, etc.    This is an inherent issue with any firmware design.  You have an external part that a FPGA is trying to interface - the FPGA compiles and generate a bit file -  and can generate different routes depending on how much has chagned, right?  Those routes changes the delay of the lines to the FPGA.  It's an inherent issue in any FPGA design when interfacing with an external device.  We provide a way to be able to program it with software with the firmware to tune the delay.  There is  plan to do it automatically in firmware in the future.

Anyways, from what we have done, the hardware of your FMC151 is working, it's just the tap delays needed to change from the default value in software.  If you need to change the frequency, you'll need to look at the ADC configuration in software and you'll need to build the software yourself.

We can support you on using our reference software and reference firmware but beyond that you'll need to contact sales@4dsp.com.


Tony





Hello,


Is there a way to fix these problems by slowing down the sampling frequency, let say from 247 MSPS to 10 MSPS.


My application does not require very high sampling rate and hence, I could still work with a slower frequency if that could fix the problem.


Paul
Please open a new topic on this.  As far as the tap delay, please see the previous posts.  It is designed to sync the lines of the clock and the adc traces to the FPGA's logic.



[quote author=samar link=topic=2922.msg15800#msg15800 date=1401738354]
Hi,

I am a collaborator working with Paul on this design. I think it might help to provide some context for this problem.

We are trying to generate a 500 Hz square wave from the DAC, and integrate over part of the response from a circuit. The generation seems to work seamlessly. The integration should be done over 50K samples from the ADC, 0.1 ms after the positive edge, for each period of the generated signal.

We modified the reference VHDL, but during synthesis in ISE, we are having difficulty meeting timing. So, there are two issues:

1. Which signal(s) should we extract from the given design to get the ADC outputs?
2. What tap delay should we use, and how should we insert it directly in the VHDL logic?

Thanks!
[/quote]
Hi,

I am a collaborator working with Paul on this design. I think it might help to provide some context for this problem.

We are trying to generate a 500 Hz square wave from the DAC, and integrate over part of the response from a circuit. The generation seems to work seamlessly. The integration should be done over 50K samples from the ADC, 0.1 ms after the positive edge, for each period of the generated signal.

We modified the reference VHDL, but during synthesis in ISE, we are having difficulty meeting timing. So, there are two issues:

1. Which signal(s) should we extract from the given design to get the ADC outputs?
2. What tap delay should we use, and how should we insert it directly in the VHDL logic?

Thanks!

While it's possible to add delays to the firmware, you'll have to recompile it several times to get the right timing iwth hardware, right?  That's a significant amount of time to spend on it.

Our reference design utilizes software and firmware so that certain things such as delays in the line which may vary amongst different hardware platforms and configurations can be done directly in software without having to recompile firmware. 


Thank you.


But is it possible to slow down the clock directly in the ISE project (which is created by Steller IP with no modifications of default design from 4DSP for ML605) so as to synchronize the clock with the data.


regards,
Paul

Well, you will need to tune your design to the right delays.

basically, the lines coming in from the ADC going into the FPGA - there is a clock and the signals.  The delay adjust the clock so that it syncs up with the bits coming from the ADC.  If it's not synchronized, then you'll see the issue.    I'm just making sure the hardware doesn't have problems - there could be issues in your design that can result in the signal that you have sent me earlier (as well as in our refernece deisgn which may be addressed since the leeway is a bit tight).

In our design, the software tune the delay by writnig a value to the FPGA and the FPGA adjust the delay of the ADC signals coming in.  Your design may be different.


Go ahead and give the app with delay of 26 a try and with our default reference firmware and your current hardware setup,  you should see good signals in loopback.  Then you can use a signal generator and should see decent results.




Hello,


So I guess, I will run this .exe file and then I download my custom design (which has some added modules for the reference design) and continue with my work.


So now, the values that I observe in chipscope is assumed to be correct. Right?


regards,
Paul
Hi,

Attached is the Fmc15x for tap delay 26.  You should get decent results now with this on your current hardware setup.

Peter will probably get back with you on the resolution for this issue in the long run.  In your code you'll need to account for the delay - our reference code for your current platform will need to change to:

case CONSTELLATION_ID_ML605:
    case CONSTELLATION_ID_FMC151_ML605:
        printf("Found ML605 hardware\n\n");
      [b] tapiod_clk = 26[/b]; tapiod_data = 0x00;
        break;



Paul

can you check file #26?  I believe that delay looks good on your board.

I'll need to check with our firmware guys to see what's going on.

Tony
Hello,


I have uploaded the zip file which has all the 32 files.


Paul

After the run, you should see:

adc0_tapioclk_0.txt to adc0_tapioclk_31.txt files

then the same for adc1.    Go ahead and RAR or zip up all the files and I can take a look.  The delay range can be narrow apparently.