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Noise with FMC151

Hello,


I am trying the reference design provided with ML605 and FMC 151. I am generating a 5MHz sine wave with an amplitude of 1V. I am communicating with the board with Ethernet.  I am using the following cable to connect the FMC 151 (MMCX) with a signal generator : http://www.pasternack.com/mmcx-plug-bnc-female-rg174au-cable-assembly-pe36738-48-p.aspx


The waveform obtained with noise is attached with this post. I was wondering if the board would have so much noise in the waveform. I also noticed that the board is becoming much warmer IC. Is this normal?


regards,
Paul




Second set of text files :



Hi Paul,

Thanks for the correction.

Here are two more sets of delays (27 and 22).  Basically the default app has 0 delays and I am trying to figure out if going forward 5 to 10 or back wards -5 to -10 change the received. 

Please let me know which set corresponds with which delay, it'll help the process. 


Hello,


Please find the text files for tap 22:


Also, note that I changed to a new ML605 board, but of the same type and version .


Paul



Please find the text files for tap 27:


Paul
Hi Paul,

Attached is the log file that i see when I run the application - you should see the SAME settings (voltage and frequencies) - please verify that this is what you see using the provided application (in the c:\program files\) as well as what i gave you (the list of delays).

I tried the application with the firmware and at tap delay 0, and tap delay 10.  As you can see, tap delay 10 is bad, but tap delay of 0 is good (the default value). 

I'll try to get an applicatio nto you that will create 31 differnet cases in a long loop that will try each tap delay.  You can use Visual Analog as well to verify the results.  IDEALLY though you guy sshould be doing this and setting the tap delays because it's dependent on the board that you're using (trace length, etc. will affect it).




Here is the log file.  Please verify this is the same as what you see on your screen.
Yes.


Log files are identical except that the number of devices is 6 in my log file instead of 3 and the temperature is 29 instead of 39.


Paul

Hi John,

Attached is a new binary file - this one will go through all 32 available tap delays (0 to 31) and save adc0 and adc1 into 32 different txt files.  Please RAR the resulting files with the loopback after you're done.

This allows us to see if there is any value that will result in correct signal.

Tony

After the run, you should see:

adc0_tapioclk_0.txt to adc0_tapioclk_31.txt files

then the same for adc1.    Go ahead and RAR or zip up all the files and I can take a look.  The delay range can be narrow apparently.
Hello,


I have uploaded the zip file which has all the 32 files.


Paul
Paul

can you check file #26?  I believe that delay looks good on your board.

I'll need to check with our firmware guys to see what's going on.

Tony
Hi,

Attached is the Fmc15x for tap delay 26.  You should get decent results now with this on your current hardware setup.

Peter will probably get back with you on the resolution for this issue in the long run.  In your code you'll need to account for the delay - our reference code for your current platform will need to change to:

case CONSTELLATION_ID_ML605:
    case CONSTELLATION_ID_FMC151_ML605:
        printf("Found ML605 hardware\n\n");
      [b] tapiod_clk = 26[/b]; tapiod_data = 0x00;
        break;



Hello,


So I guess, I will run this .exe file and then I download my custom design (which has some added modules for the reference design) and continue with my work.


So now, the values that I observe in chipscope is assumed to be correct. Right?


regards,
Paul

Well, you will need to tune your design to the right delays.

basically, the lines coming in from the ADC going into the FPGA - there is a clock and the signals.  The delay adjust the clock so that it syncs up with the bits coming from the ADC.  If it's not synchronized, then you'll see the issue.    I'm just making sure the hardware doesn't have problems - there could be issues in your design that can result in the signal that you have sent me earlier (as well as in our refernece deisgn which may be addressed since the leeway is a bit tight).

In our design, the software tune the delay by writnig a value to the FPGA and the FPGA adjust the delay of the ADC signals coming in.  Your design may be different.


Go ahead and give the app with delay of 26 a try and with our default reference firmware and your current hardware setup,  you should see good signals in loopback.  Then you can use a signal generator and should see decent results.




Thank you.


But is it possible to slow down the clock directly in the ISE project (which is created by Steller IP with no modifications of default design from 4DSP for ML605) so as to synchronize the clock with the data.


regards,
Paul