HI

You are correct.

an interpolation of 4 means that the output data rate is 4 times faster as the input rate. Therefore the DAC output clock should be 4 times the digital input data rate.

The FPGA to DAC interface transfers data for both the channel A and the channel B as well as two bytes per channel. This is 4 bytes so therefore the data rate on the digital data bus has to be 4 times the actual sample rate.

best regards,

Erik

You are correct.

an interpolation of 4 means that the output data rate is 4 times faster as the input rate. Therefore the DAC output clock should be 4 times the digital input data rate.

The FPGA to DAC interface transfers data for both the channel A and the channel B as well as two bytes per channel. This is 4 bytes so therefore the data rate on the digital data bus has to be 4 times the actual sample rate.

best regards,

Erik

## Customer

ADC_CLK_P/N (driven by CDCE to ADS62P49): 245.76MHz

CLK_TO_FPGA_P/N (driven by CDCE to FPGA): 245.76MHz

DAC_CLK_P/N (driven by CDCE to DAC3283): 491.52MHz

DAC_DCLK_P/N (driven by FPGA to DAC3283): 245.76MHz

Are those frequencies correct?

From what I have learned from the VHDL firmware code (dac3283_phy.vhd) it appears that a new *pair* of samples (i.e. 1 sample for each of the DAC's outputs) is written out to the DAC from the FPGA at a rate of 122.88MSps. Similarly, the DAC outputs a pair of samples on the analog side at the same rate of 122.88MSps since the DAC3283 is configured for an interpolation factor of 4x which divides the DAC_CLK_P/N frequency by 4. Is this correct?

In addition, with the configuration of the OSERDES (in dac3283_phy.vhd) a new byte (i.e. half-sample) is written into the DAC data interface at an effective rate of 491.52MHz due to a new byte being written out on both the rising and falling edge of the DAC_DCLK_P/N (which is 245.76MHz). Is this correct?