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FMC176 : JESD204B Lane configuration

Dear Sir/Madam,
I am using FMC176 board of 4DSP. When I look at the file FMC176_adc.cpp, I can't not figure out the absolute address of the registers that following commands what to execute, especially the first  address [font=Verdana][size=78%]bar_adc_phy+0x00.[/size][/font]

// JESD204B Lane Configuration
rc = sipif_writesipreg(bar_adc_phy+0x00, 0x82); Sleep(10);
rc = sipif_writesipreg(bar_adc_phy+0x01, 0x01); Sleep(10); //F=2
rc = sipif_writesipreg(bar_adc_phy+0x03, 0x1F); Sleep(10); //K=32

My understanding is that these commands configure the JESD204b receiver on the FPGA  with 2 octets/frame and 32 frames/multiframe. But I cannot work out what the first command will do because it does not have an included comment.
Could you please advise?


The write to address 0x00 indeed configures the receiver in the FPGA. Value 0x82 translates to (bit 7 downto 0 = 0x82):
- bit 1: enables receiver support for lane sync
- bit 7: writing a '1' to this bit generates a reset pulse for the receiver logic

Best regards,
Ingmar van Klink

thank you very much for your explanation.
Dear Clive,

Please let me know if you need anything more about this issue, if not I will close this topic in 24 hours.

Best Regards,
This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.