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ADC timing for GTX on VC707

Hi all,


I'm trying to integrate the FMC176 into a design outside of Stellar IP on a VC707 board. I'm trying to implement GTX transceivers (using the 7 series transceivers wizard) and I have a few questions. Under the usual run conditions for the board (from the example design):


-What frequency clock is available at REFCLK0?
-What data rate are the JESD204B lanes running at?
-What pins correspond to the JESD204b lanes for ADC0, lane 0?


From what I can gather, the reference clock should be 125 MHz, the data rate 5 Gbps, and the serial lanes should be at pins D7 and D8 (which is GTX channel X1Y24). Is this correct?

Dear Sir,


The reference design is complete. As soon StellarIP generates  you get a whole ISE project which contains RTL, UCF and project settings and yield into a design operating fine. Firmware ID 348


Best Regards,
Arnaud
And it's an excellent example design, but it doesn't quite fit my specifications. To fit these specifications, I am trying to incorporate the board into a new design. Although I have a new design, it is not working. It may not be working because I do not understand  the original design (for instance, I may have misinterpreted a constraint). To see if I understand your design, I am asking questions about it.


I'm not asking without having tried everything I can think of with the files that came with the board. I have been unable to port the example over to my new design, and I'm going through a lengthy and intensive debugging process to attempt to establish where the error is, so I may begin to fix it. Any help you can offer, even if it is just a simple "yes" or "no" to my question, would be greatly appreciated.
Dear Matt,


I will get a firmware engineer to review this post, he can probably come up with quick answers.


Best Regards,
Arnaud
Hello Matt,


[quote author=mattgran link=topic=2402.msg12440#msg12440 date=1383068533]
-What frequency clock is available at REFCLK0?
-What data rate are the JESD204B lanes running at?
-What pins correspond to the JESD204b lanes for ADC0, lane 0?

From what I can gather, the reference clock should be 125 MHz, the data rate 5 Gbps, and the serial lanes should be at pins D7 and D8 (which is GTX channel X1Y24). Is this correct?
[/quote]


Yes, it's correct. If you open the gtx coregen file, you can see that data rate is 5Gbps and reference clock is set to 125MHz. FMC DP[0:3]_M2C are connected ADC[0:3].


Thanks,
Kyu
I am also working with FMC176 and VC707 and having problem with the relationship between the serial line rate and the ADC sampling rate. Could anyone kindly explain to me that relationship? It is sampling rate of ADC 1/40 of the serial line rates?

Thanks,


Dear,


The serial link rate depends on the ADC sample clock frequency and number of lanes and channels. The relation is (refer to the datasheet of the AD9250):
Serial rate = 1/(L/(20*M*Fs))
with:
Fs = Sample frequency
M = Number of converters
L = Number of serial lanes


By default we set the ADC sample rate close to 250MHz and use both ADCs and both Lanes inside the chip. This results in a link rate of 5Gbps.
If you are changing the sample rate you should also make sure that the MGT reference clock is configured properly, this is OUT4 of the AD9517 clock generator (see FMC176_clocktree.cpp of the reference software). You have to configure clock OUT4 to a frequency which you also have to set as the reference clock frequency in the core_gen transceiver wizard. The last step is to configure the link rate of your transceiver according to the formula above.


Best regards,
Ingmar van Klink

Dear Sir,


Was the information sufficient? Can I go ahead and close this topic?


Best Regards,
Arnaud
This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.