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SPI control timing diagram

On page 16 of the FMC 176 User Manual, several timing diagrams are given for the register read/write operations. As far as I can tell, these diagrams are indicative of a clock polarity of 1 and a clock phase of 1. However, these timing diagrams also appear to indicate an additional clock cycle on the output clock after the operation completes, which is not included in the SPI standard. Am I reading the diagram wrong?
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There is no additional clock cycle. Once N_CS is high, SCLK and SDIO become don't cares.

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