Hello, My company bought the FMC176 board and the ZC706 board. Register 0x01F on AD9517 reads back 0xE on SPI communication, meaning that neither VCO, ref1 or ref2 are within frequency threshold and PLL is not locked. I need to configure the board to output a reference clock to the FPGA for the GTX of the ADC. I tried different register settings with no success. PLL readback from AD9517 always gives 0xE. I want to know what registers I need to configure to get it working.
Dear Sir, I assume we do not have reference design for ZC706. You could contact sales to enquire about its availability. This is a complex hardware you will need a reference design in order to use. I recommend you to procure a supported carrier and refer to the reference design. Best Regards, Arnaud
about 4 years ago
Ok, I downloaded the reference design and looked into the code and found some registry settings. I put those on the board and got a clock on pins D4 and D5 (not H4 and H5 as was written in the user manual). The clock frequency is not the right one since register 0x01F of AD9517 is sometimes E sometimes F. This means that PLL locks most of the time, but also that VCO, ref1 and ref2 are outside the frequency threshold. I measured the frequency with an oscilloscope and got 242.5MHz instead of 245.76MHz (value that the reference design says it should give).
I need to have a stable frequency at 245.76MHz, how do I get that and why do the base design settings don't give a stable clock at the right frequency?
Alex. P.S. I looked at the vhdl and I have two comments. 1st, why is there no VHDL version, 2nd in the UCF file of the system there are no FPGA pins mapped to FMC pins H4 and H5 so please check the user guide pinout.
about 4 years ago
1. It can be an internal reference clock to the AD9517. Could you make sure to turn on the "REF_EN" and check the reference clock? REG_EN is a reg0 in the CPLD. You can probe it on R40 or R43. This should generate 30.72MHz. 2. When internal VCO is used, there is a "calibration" cycle required in the AD9517. If this is not implemented, then the frequencies might be close, but the PLL might not lock. When you read 0x01F, bit6 should be '1'.