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Generate Full FPGA code

I have read over the forums and documentation and had a question on working off of 4dsps design.  My project has to do with interfacing with the FMC 204 design.

Looking at the Stellar IP blocks for the reference design it seems to be me that if I delete all of the blocks except sip_fmc204 block, I can use that to generate my main code.  Is this true?

Also, if this is true does this mean that I just need to sync my data with the DAC#_DACCLKN/P?

I did have a question on the CLK_TO_FPGA_N/P seems to just be referenced to an external source.  If this is true does that mean that my internal clock would be the main sync for data and the DAC clock?

Thanks in advance.

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.
Dear Sir,


We are always delighted to help when we can.


Feel free to open new topics anytime you need that done!


Thanks,
Arnaud
Yes I appreciate the answers and prompt replies.

Thank you,

Dear Sir/Madame,


Was the information sufficient, can we proceed with closing this topic?


Best Regards,
Arnaud
[i]What I was saying if I used my own command send block to sip_fmc204 block in Xilinx, would I just need the sip_fmc204 block in IP STELLAR to just generate code and use that to reference from.[/i]

Yes.

This document might help you with that:[color=#1F497D]
[url=http://www.4dsp.com/pdf/AN002_StellarIP_Interface_to_AXI_Interface.pdf]http://www.4dsp.com/pdf/AN002_StellarIP_Interface_to_AXI_Interface.pdf[/url][/color]

[i]I am trying to figure out what my clocking needs to be set for that SPI communication and what kind of delay between each send command?[/i]

Those requirements are in the DAC datasheet, it is whatever the device can support. SPI communications is implemented in fmc204_cpld_ctrl.vhd, so you should just send StellarIP commands exactly like the reference application does them.  You need to do commad + delay + command, because you can't send StellarIP commands one after another, especially when doing a read. It takes more than 1 command clock cycle to send the command and get it back because the SPI clock is a divided version of the command clock.



What I was saying if I used my own command send block to sip_fmc204 block in Xilinx, would I just need the sip_fmc204 block in IP STELLAR to just generate code and use that to reference from.

Also, on the CPLD SPI communication what is the timing requirements for that clock as the user manual does not say what the timing constraints are.  I am trying to figure out what my clocking needs to be set for that SPI communication and what kind of delay between each send command?

command = [pre-selection byte + bit instruction + register data]

command + delay + command
            OR
command + command
[i]
Looking at the Stellar IP blocks for the reference design it seems to be me that if I delete all of the blocks except sip_fmc204 block, I can use that to generate my main code.  Is this true?[/i]

Not sure what you are trying to do, but in general yes each block can work independently and other customers have done that if theyan AXI system. You still need some sort of master/host interface to send commands that will configure the FMC clock tree and devices.

[i]Also, if this is true does this mean that I just need to sync my data with the DAC#_DACCLKN/P?[/i]

Yes you need to be on the clock domain of the DAC to send data out to the DAC, those clock come out of the FPGA. In some DACs those clocks are inputs but here they are outputs so they are generated by the FPGA.


[i]I did have a question on the CLK_TO_FPGA_N/P seems to just be referenced to an external source.  If this is true does that mean that my internal clock would be the main sync for data and the DAC clock?[/i]

Look at the clocking tree in the FMC204 User Manual. There is a clock chip that sends a clock to the DACs and the FPGA so that all devices get the same clock. The FPGA uses that clock to send data and a clock to the DAC. You have to be in that clock domain when sending data to the DAC.