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SPI Configure Interface

[font=arial]Hi, i’m connecting FMC230 to ML605 using LPC. I wrote a DAC interface module in VHDL like this:[/font]

[font=arial]entity DAC_Interface is[/font]
[font=arial]  Port ( [/font]
[font=arial]    dac_clk      : in  std_logic;                    -- Master input clock from DAC[/font]
[font=arial]    wr_clk        : in  std_logic;                    -- Write clock for data[/font]
[font=arial]    rst_system  : in  std_logic;[/font]
[font=arial]    ref_clk    : in  std_logic;                    -- Reference clock to IDELAY CONTROL[/font]
[font=arial]    clkdly_clk  : in  std_logic;                    -- idelay INC/DEC CLK must be always on[/font]
[font=arial]    clkdly_inc  : in  std_logic;                    -- idelay INC/DEC[/font]
[font=arial]    clkdly_ce  : in  std_logic;                    -- idelay INC/DEC enable[/font]
[font=arial]    input_data_even_0    : in  std_logic_vector(13 downto 0);[/font]
[font=arial]    input_data_even_1    : in  std_logic_vector(13 downto 0);[/font]
[font=arial]    input_data_even_2    : in  std_logic_vector(13 downto 0);[/font]
[font=arial]    input_data_even_3    : in  std_logic_vector(13 downto 0);          [/font]
[font=arial]    input_data_odd_0      : in  std_logic_vector(13 downto 0);[/font]
[font=arial]    input_data_odd_1      : in  std_logic_vector(13 downto 0);[/font]
[font=arial]    input_data_odd_2      : in  std_logic_vector(13 downto 0);[/font]
[font=arial]    input_data_odd_3      : in  std_logic_vector(13 downto 0);                                                                  [/font]
[font=arial]    clk_out                    : out std_logic;          -- DDR clock to DAC[/font]
[font=arial]    data_even_out        : out std_logic_vector(13 downto 0);[/font]
[font=arial]    data_odd_out          : out std_logic_vector(13 downto 0)                    [/font]
[font=arial]    );[/font]
[font=arial]end DAC_Interface;[/font]

[font=arial]I also finished the UCF-file according to the LPC pin-out provided in FMC230 User Manual. Now I need an SPI module to configure the DAC. An external sampling clock >= 2.8GHz should be used for synchronization with the ADC which is connected on the HPC. Could you tell me how I can get this SPI module efficiently? Thank you![/font]

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.
Dear Sir,


I am delighted to hear about this leap forward. I will close this topic and please feel free to open any new topics, would you require to do so!


Best Regards,
Arnaud
Hello,

I have integrated "fmc230_if.vhd" in my top module. I removed the instances that are not needed, so that just "fmc230_cpld_ctrl", "fmc230_ad9129_ctrl" and "fmc230_ad9517_ctrl" are used. I'm now implementing an FSM to write the register settings in "in_cmd" zu configure the DAC. I hope it will work.

Regards,
Ge
Dear Sir,


Have you been able to move forward on this topic?


Thanks,
Arnaud


Hello,


Once again the FMC230 reference design is perfectly able to configure the DAC, so the SPI module in the reference design is operating just fine, please refer to the reference, which is delivered as source code and with documentation.


As explained already, StellarIP will not generate IP core but use IP core to generate a firmware, which in this case contains the FMC230 star.


You could decide to also ask 4DSP to provide you with the reference design you need, a one channel DAC on ML605 LPC. If this is a path you are willing to take, let me know and I will get one of our sales engineer to get in touch with you.


Best Regards,
Arnaud




















[size=3][font=arial]Hi Arnaud,[/font][/size]
[size=3][font=arial] [/font][/size]
[size=3][font=arial]Can I describe my problem a little bit?[/font][/size]
[size=3][font=arial] [/font][/size]
[size=3][font=arial]in my system I work on a ML605 FPGA board. An ADC is connected on the HPC for sampling data. The FM230 is connected on the LPC as one single DAC. A signal processing is done in the FPGA before the data goes to the DAC. The ADC and DAC shall share one external clock of ca 2.8 GHz.[/font][/size]
[size=3][font=arial] [/font][/size]
[size=3][font=arial]I finished the configuration of the ADC and the signal processing and also wrote a dac_module (PHY) and a SPI master to configure the CPLD using the register mapping in FMC230 User Manual. The ADC board works but the FM230 does not. I think the main problem is on the SPI module, and that was the reason why I’m looking for a solution to generate an SPI configure module as an IP core from your StellarIP.[/font][/size]
[size=3][font=arial] [/font][/size]
[size=3][font=arial]Do you have more advice for me?[/font][/size]
[size=3][font=arial] [/font][/size]
[size=3][font=arial]Regards,[/font][/size]
[size=3][font=arial]Ge [/font][/size]
Hello,


Well as soon you generate the firmware you will get a complete ISE project with all the interfaces and UCF, you can easily navigate the firmware in ISE Navigator and you can also run simulation on it. You should not take shortcuts here.


You have a complex chipset and it will be faster to use the usual approach:


1) Run the reference design.
2) Modify the reference design for your needs.
3) Move onto the integration efforts.


Typically our customers are not reinventing the wheel constantly (well some does, of course) but they would more look into reusing our FMC230 star into their project because this makes sense.


StellarIP does not generate modules, it does generate ISE projects using stars but obviously, the software is able to configure all the integrated circuits through the firmware so obviously the firmware is perfectly able to communicate with these integrated circuits.


I really hope that helps,
Arnaud



[font=arial]Hi Arnaud,[/font]

[font=arial]I don't need the complete firmware. Can I only generate the SPI module with the help of StellarIP?[/font]

[font=arial]Regards,[/font]
[font=arial]Ge[/font]
Dear Sir,


Firmware 337_ml605_fmc230 is a complete ISE firmware as soon it is generated from StellarIP. A complete working firmware for your board combination, this is the actual reference design.




Best Regards,
Arnaud



[size=3][font=arial]Hi Arnaud,[/font][/size]
[size=3][font=arial] [/font][/size]
[size=3][font=arial]Thank you for your answer! I found a reference design “fmc230_if.vhd” in this folder:[/font][/size]
[size=3][font=arial] [/font][/size]
[size=3][font=arial]C:\Programme\4dsp\Common\Firmware\Extracted\337_ml605_fmc230\star_lib\sip_fmc230\vhdl[/font][/size]
[size=3][font=arial] [/font][/size]
[size=3][font=arial]Can you have a look at it and tell me is that the one you meant?[/font][/size]
[size=3][font=arial] [/font][/size]
[size=3][font=arial]Thanks,[/font][/size]
[size=3][font=arial]Ge[/font][/size]
Dear Sir,


I am not sure which SPI module you should use but maybe it would make sense to look at the reference design, it is provided as source code for both the software and the firmware. The reference design is able to completely configure the chipset during runtime; So the SPI communication is done there.


Best Regards,
Arnaud