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Synachronization of two DACs' output

[font=calibri]With your information, FMC230 has been brought up on our in-home FPGA system, with external ref mode of 54MHZ crystal clock.  I appreciate your help very much.[/font]
[font=calibri]Currently, I am moving to the next step. Since that being used in wireless communication,  I am trying to sync the analog output from DAC0 and DAC1 on FMC 230 for our case.  But there are a few questions I am asking.[/font]
[font=calibri]1.[/font]      [font=calibri]I generated sin wave within our host system as test data pattern for FMC230.  The two channels of clean output could be probed on the scope with the basic initialization sequence I learned from your reference C code.  But what we observed is that there is large phase difference between analog outputs from DAC0 and DAC1, around 20ns, and both of DACCLKs in our case is 625MHZ.  I feel confused about it, because the inner fifos just have the depth of 8, why the phase difference is like this?[/font]
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[font=calibri]2.[/font]      [font=calibri]In order to sync the two channels of output, I follow datasheet of AD9219, and tried to use frame signal initializing the fifos of DACs at first. The details are shown in the attached picture (AD9219 datasheet p50).[/font]
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[font=calibri]But the modification didn’t cause any obvious reduction happening for the phase difference of two DAC chips’ analog output.  I am not sure if my current  actions for frame signal is correct or sufficient, is there any more register settings needed for initializing the fifos in DACs?    [/font]
[font=calibri]I know the sync part is pretty tricky. [/font][font=calibri]Have you done any experiment for syncing dac outputs on FMC230 board before it was released, even though I know the current fpga build on ML605 doesn’t include the functionality of dac output sync.  Or, could you give me any suggestions or information regarding the synchronization of DACs output.[/font]
[font=calibri]Thank you[/font]

Dear Jerry,

You have a custom FMC230 board with the custom option (C64) routing SYNC pad to the FMC connector and you are trying to achieve that with FPGA?

I have briefly looked at the modification procedure and it involves testing the patch with an ohmmeter so we do not have specific reference test.

It would be best to ask Analog Devices for this question, we just know that the connection to SYNC pad are valid.

Best Regards,

[font=Verdana]Hi Arnaud,  [/font]

Thanks for the reply.

Yeah, I am trying to  implement the SYNC control for FMC230 on our FPGA system.

That's ok, I will contact Analog Device for the question.


Dear Jerry,

Perfect, thanks for the feedback, I am closing this case the issue being resolved.

Best Regards,