Start a new topic

Reference Design Details


Fmc30RFAPP:


There is one specific command line parameter for this reference design: clock mode. It determined whether the TX CLK and RX CLK connectors are used as input or output. The TX CLK and RX CLK connector can generate or accept the carrier frequency for the TX path and RX path respectively;
0. Both TX CLK and RX CLK are output, the carrier frequency is generated by the onboard synthesizers
1. RX CLK is output, the carrier frequency is generated by the onboard synthesizer (TRF3765). TX CLK is input, the carrier signal can be supplier from an external source.
2. TX CLK is output, the carrier frequency is generated by the onboard synthesizer (TRF372017). RX CLK is input, the carrier signal can be supplier from an external source.


The early application does the following:


- Initializing the Ethernet communication
- Reading the CID information; firmware IDs, number of stars, etc..
- Reading/Computing base offset of all the firmware stars in the constellation.
- Detecting the FMC board.
- Display voltages.


The application then focus on the FMC30RF chipset. At first the different devices on the FMC30RF are initialized:
- The TRX switch is forced into FDD mode, which means the RF IN/OUT connector is used as an output only
- The 2nd LNA stage is disabled. The 1st LNA stage is always enabled. The gain is approximately 18dB per stage.
- The attenuator is set. The range is from 0 to 31 (1dB steps) with 0 being maximum attenuation.
- The CDCE62005 is initialized first, since this is the base clock generating references to other parts of the design;
o The PLL is setup for a VCO frequency of 983.04MHz
o OUT0 connects to the FGPA and divides by 4 (245.76MHz)
o OUT1 connects to the AFE7225 and divides by 4 (245.76MHz)
o OUT2 connects to the TRF3765 and divides by 32 (30.72MHz)
o OUT3 connects to the reference clock output and divides by 32 (30.72MHz)
o OUT4 connects to the TRF3720xx and divides by 32 (30.72MHz)
- The TRF3711xx is initialized as per datasheet. Since the FMC30RF comes in two different ranges, the range is detected by reading the device ID of the TRF3711;
o TRF371109: FMC30RF range 1 (300MHz to 1200MHz)
o TRF371125: FMC30RF range 2 (1200MHz to 3000MHz)
- The TRF3765 is initialized as per datasheet. The synthesizer determines the carrier frequency for the RX path and settings depends on the range:
o FMC30RF range 1: 525MHz
o FMC30RF range 1: 2100MHz
- The TRF372017 is initialized as per datasheet. The synthesizer determines the carrier frequency for the TX path and settings depends on the range:
o FMC30RF range 1: 525MHz
o FMC30RF range 1: 2100MHz
- The AFE7225 is initialized as per datasheet. This is the dual A/D, dual D/A and there are some specific setting required to match the frequency plan:
o The clock coming from the CDCE62005 is 245.76MHz, therefore:
o The interpolation factor is set to 2, to allow for a digital DAC rate of 122.88Msps
o The ADC clock divider is set to  2, to allow for a digital ADC rate of 122.88Msps
- During the initialization of the AFE7225, the FPGA needs to properly align to the serial links. The FPGA firmware in the reference design will do this semi-automatic, following the step:
o Enable custom ADC pattern in the AFE7225; set to b’000111000111’
o Reset clock buffer and iDelays in the firmware
o Reset iSerdes in the firmware
o Start training in the firmware; the firmware will automatically adjust input iDelays and perform Bitslip to align the serial links
o Disable custom ADC pattern in the AFE7225


Now the FMC30RF is setup and reference application will be:


- Taking a snapshot of samples from the RX path (maximum size depends on FIFO size implement in the FPGA and may vary from design to design).
- Upload a snapshot of samples to the TX path (maximum size depends on waveform memory (WFM) size implement in the FPGA and may vary from design to design). The snapshot is repeatedly played through the TX path.
- The data format is 14-bit, 16-bit left aligned complex samples with I and Q samples interleaved.


One way to use the reference application can be used is to connect an antenna to the RF IN/OUT and an antenna to the RF IN. The reference application makes sure the TX path is transmitting the waveform prior to taking a snapshot from the RX path. This way, the FMC30RF captures the self-generated signal (loopback).


Yes, look at the CDCE62005 datasheet and at the function

 int32_t fmc30rf_cdce62005_init(uint32_t bar, uint32_t clocksource)

 

in the FMC30RFAPP source code.

Hi,


It is said that:

"The CDCE62005 is initialized first, since this is the base clock generating references to other parts of the design;

o The PLL is setup for a VCO frequency of 983.04MHz"


In our setup we are working in between 900 - 2000MHz and we see a signal at 983.04 MHz whic is the  VCO frequency of 983.04MHz. Is there any way to reduce the VCO clock to 983.04/2=  491.52 MHz?


Can the frequency value of VCO PLL be controlled via register setting?


Regards,


Cemal

Login or Signup to post a comment