It is said that:
"The CDCE62005 is initialized first, since this is the base clock generating references to other parts of the design;
o The PLL is setup for a VCO frequency of 983.04MHz"
In our setup we are working in between 900 - 2000MHz and we see a signal at 983.04 MHz whic is the VCO frequency of 983.04MHz. Is there any way to reduce the VCO clock to 983.04/2= 491.52 MHz?
Can the frequency value of VCO PLL be controlled via register setting?
in the FMC30RFAPP source code.