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fmc30rf transmit

I'm trying to send my own I Q samples (generated in hardware) into the AFE7225 (DAC). The samples are being clocked out at the fabric clock rate (125 MHz). The I Q samples have a carrier frequency that's arbirtrarily set by me. I've been testing with 1 MHz.  I'm setting LO_TX to 1575 (1.575 GHz?) in the initialization of the trf3720 (IQ Modulator).

I naively connected up my sample generator to the afe7225_phy instance. That is, I'm directly feeding tx_data_i (16 bit), tx_data_q (16 bit) and being admittedly ignorant (stupid?) about clock control in the fmc30rf_if.

At the RFIO mmcx port I'm seeing my 1.575 GHz with some kind of added noise from my I Q samples. I know this because I get a perfect 1.575 GHz sinusoid when tx_data_i and tx_data_q are zeros, whereas when they are non-zero I see the noise modulated on top of the 1.575 GHz. What am I really seeing? I don't understand what I'm seeing because I don't understand the clock control in the fmc30rf_if and because I don't very well understand what the trf3720 is doing.

When I measure the on-board frequencies, I see [i]DAC PHY Clock[/i]; what exactly is [i]DAC PHY Clock[/i]? Do I read that as DAC Physical Clock? Is it a measurement of the physical clock going to the DAC? Is it the DAC sampling frequency?

How does DAC PHY Clock relate to [i]tx_clk[/i] of the fmc30rf_if? How do those clocks relate to dac_dclkin, dac_fclkin, dac_syncin?

Is there a block diagram that goes into more detail of the fmc30rf HDL + afe7225 + trf3720?

Is what I'm trying to accomplish not feasible?

Dear Stuart,

First of all, are you able to run the reference design? Does that work fine?

There is some extra details about the reference design found there :,1629.0.html

The TRF3720 datasheet can be found there :

As far as the FMC30RF clocking is concerned, you can check the FMC30RF user manual, chapter 5 and more details on the control on chapter 6.

Another tip would be to verify validity of your settings using TI software you can download from their websites.

I hope that helps

Best Regards,

Yes, the reference design works fine for me on my zc706. The reference design also works on my zc702, after changing fmc30rf_ctrl_probefmc() to handle the correct return dword (2) from hardware.

For understanding how clocking works in the fmc30rf, chapter 5 and 6 of the user manual is insufficient. I need more detail.

I refer you to my question one more time:

How does DAC PHY Clock relate to [i]tx_clk[/i] of the fmc30rf_if? How do those clocks relate to dac_dclkin, dac_fclkin, dac_syncin?


fmc30rf_ctrl_probefmc() expect the GPIO switch to be set properly (GPIO_DIP_SW0 to "0" on SW12) on both ZC702/ZC706, check 4FM Getting Started Guide. That should work fine.

I have the feeling to repeat myself again, but please refer to the reference design; The FMC30RF is too complex to document everything, you will need to understand the reference design, modify the reference design as any of our customer did using the same material. There is also information on a sticky topic in the FMC30RF forum.

If you are not able to do so, we can offer you an engineering support contract, where we will help you and answer all your direct questions. If this is a path you are interested to take, I can get a sales engineer to discuss that further with you.

Best Regards,
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Dear Stuart,

I am following up with you, you haven't reported back to me, do you want me to get a sales engineer to contact you to discuss that further?

Best Regards,
No, I guess you can close this thread.
This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.