Start a new topic

Details about on-board reference clock

Can you share any details regarding the on-board reference clock on this card? Can you provide the part number? Is it just a 30.72 MHz crystal oscillator or something that is programmable/configurable? Thanks.


Edit: Also, when I run the demo application, I get an ADC PHY clock at 307.21 MHz, a DAC PHY at 307.19 MHz, and a CDCE62005 Spare at 614.4 MHz. The SD111 FMC30RF Star documentation shows that the ADC/DAC PHY clocks should be 368.64 MHz? And the post on this board on the reference design details suggests that the output from the CDCE60025 to the FPGA should be 245.76 MHz? Can you help shed some light on this situation?

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.
Dear Sir,


I have checked both reference designs and the clocking scheme is different. On the Zedboard-FMC30RF design (Avnet reference design), everything is clocked on FCLK0 which is set to 50MHz. In the 4DSP reference design everything is clocked on FCLK2 which is set to 125MHz.


So you can either modify the software, in order to use 50MHz for you calculation because this is what you have right now or modify FCLK0 to be 125MHz and then re export the design to SDK so you get an updated ps7_init.tcl file. The booting of the Arm, including setting PLLs is done by this tcl file. In your case you changed FCLK0 to 125MHz but you have not exported to SDK, so you were still using the old ps7_init.tcl setting up FCLK0 to 50MHz, I guess it now makes sense. Everything works fine on 50MHz besides the frequency display, actually the Avnet reference design only comes with a GUI to display spectrum and this is why this problem was not spotted earlier.


Best Regards,
Arnaud

In the block design for the reference firmware (when opened in Vivado anyway), the AXI interconnect is clocked via FCLK0, which is set to be 50 MHz. Is FCLK2 connected somewhere inside the VHDL that I just overlooked?
[size=2]It sounds like the AXI clock (FCLK2) is running at the wrong frequency, it should be 125 MHz that is the clock that is used as a reference. [/size][size=small][font=Verdana]This is dictated by the file called ps7_init.tcl. The software assumes the reference clock is 125 MHz (hard coded) if it is not you will get wrong readings as you are seeing. [/font][/size]
[size=small][/size]
[font=verdana, arial, helvetica, sans-serif][size=2]Maybe export the the design from ISE and use the ps7_init.tcl generated instead of the one in the reference design.[/size][/font]


[size=small][/size]
[size=small][/size]
[size=small][/size]
Okay, so to confirm that the SPI programming is functional and that the chip responds to SPI commands, I adjusted the output divider on register 0 and register 1. For example, on line 106, I made the following change:
[code]
Original
reg[0] += 0x42<<17;      //OUT0DIVRSEL; 7-bit OUTPUT DIVIDER “0” Ratio Select
New
reg[0] += 0x02<<17;      //OUT0DIVRSEL; 7-bit OUTPUT DIVIDER “0” Ratio Select
[/code]
This changes the output divider from /4 to /8. As expected, the reference application output does reflect this change. When I do this for register 0, which controls OUT0, I get:
[code]
--- Measuring on-board frequencies ---
Stellar IP Clock : 125.00 MHz
ADC PHY Clock    : 307.19 MHz
DAC PHY Clock    : 307.21 MHz
CDCE62005 Spare  : 307.21 MHz
--------------------------------------
[/code]
Similarly, when I do this for OUT1, which is the ADC clock, I see that the ADC PHY and DAC PHY clocks fall to 153.59 MHz.

I do not remember seeing 122.88 MHz. I could be wrong, as I've been experimenting with the board for several months, but I think it's always been 307.19 MHz.

When I made the first change, dividing the primary reference by 2 instead of 1, nothing changed. This is what I would expect, however, because isn't the 30.72 MHz reference connected to the secondary reference input on the CDCE62005?


When I made the second change, the PLL didn't lock:


[code]

C:\Program Files (x86)\4DSP\FMC Board Support Package\Refs\Software\FMC30RF\Debu
g>FMC30RFApp 2 192.168.1.10 1000 2000 2000

Connected FPGA Device Type: UNIDENTIFIED DEVICE

Start of program
--------------------------------------
Constellation ID : 316
Number of Stars  : 5
Software Build  : 0x52289304
Firmware Build  : 0x00000000
Firmware Version : 0.1
--------------------------------------


Found ZEDBOARD hardware

---  Measuring on-board voltages  ---
5.0V DAC    : OK ( 4.96V)
3.3V CLK/VDD : OK ( 3.24V)
1.8V VDD1/2  : OK ( 1.81V)
4.0V RF      : OK ( 4.00V)
5.0V TRF37xx : OK ( 4.95V)
3.3V TRF37xx : OK ( 3.25V)
3.3V TCXO    : OK ( 3.26V)
VADJ        : OK ( 2.49V)
Temperature  : 41 C
--------------------------------------

40009ce8
Using onboard reference source...
Wait for PLL lock.............
CDCE62005 PLL could not lock
Could not initialize FMC30RF.CLOCKTREE
Could not initialize FMC30RF
[/code]

Edit: You can see in the above code, the output of the print statement on line 80 is 40009ce8.
[size=2]Have you ever gotten 122.88 MHz, like when you first received the board? Or have you always seen 307.19 MHz?[/size]


[size=2]Look in fmc30rf_cdce62005.cpp where those clocks are configured. Look at lines 100, and 118, what do you see?
[/size]


[size=2]Try changing to [/size]

[size=2] reg[0] += 2<<5; //DIV2PRIY; (X,Y) = 00:3-state, 01:Divide by “1”, 10:Divide by “2”, 11:Reserved[/size]


[size=2] reg[1] += 1<<5; //DIV2SECY; (X,Y) = 00:3-state, 01:Divide by “1”, 10:Divide by “2”, 11:Reserved[/size]


[size=2]then try[/size]



[size=2] reg[0] += 1<<5; //DIV2PRIY; (X,Y) = 00:3-state, 01:Divide by “1”, 10:Divide by “2”, 11:Reserved[/size]


[size=2] reg[1] += 2<<5; //DIV2SECY; (X,Y) = 00:3-state, 01:Divide by “1”, 10:Divide by “2”, 11:Reserved[/size]


[size=2]See if those changes give you a different clock readings.[/size]


[size=2]Also on line 80, add a print statement like this to make sure you see the correct part number and are editing the correct file.[/size]

[size=2]
rc = sipif_readsipreg(bar+0x08, &dword);


        printf("%x \n", dword); //  ADD THIS LINE

[/size][size=2]
if(rc!=SIPIF_ERR_OK)













[/size]
To verify, I redownloaded the reference design from http://www.4DSP.com/avnet/Zedboard-FMC30RF.zip. I used the exact .bit file and I compiled the demo application software without making any changes. The results are exactly the same as before. The ADC and DAC PHY Clocks are 307.19 MHz and 307.21 MHz, respectively, and the CDCE62005 Spare clock is 614.40 MHz. What do you suggest?
The .bit file you attached does not work for me. The programming registers "complete" after 50%. Here is the console output:


[code]

C:\Program Files (x86)\4DSP\Zedboard-FMC30RF\Ready\033114\zedb_316>go 316_zedb_f
mc30rf.bit


C:\Program Files (x86)\4DSP\Zedboard-FMC30RF\Ready\033114\zedb_316>#convert slas
hes
'#convert' is not recognized as an internal or external command,
operable program or batch file.


C:\Program Files (x86)\4DSP\Zedboard-FMC30RF\Ready\033114\zedb_316>set x=316_zed
b_fmc30rf.bit


C:\Program Files (x86)\4DSP\Zedboard-FMC30RF\Ready\033114\zedb_316>set x=316_zed
b_fmc30rf.bit


C:\Program Files (x86)\4DSP\Zedboard-FMC30RF\Ready\033114\zedb_316># call XMD
'#' is not recognized as an internal or external command,
operable program or batch file.


C:\Program Files (x86)\4DSP\Zedboard-FMC30RF\Ready\033114\zedb_316>xmd -tcl down
load_elf.tcl zedb_host_if.elf 316_zedb_fmc30rf.bit
Xilinx Microprocessor Debugger (XMD) Engine
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
Executing user script : download_elf.tcl
Programming Bitstream -- 316_zedb_fmc30rf.bit
Fpga Programming Progress ............10.........20.........30.........40.......
..50...Done
Successfully downloaded bit file.



JTAG chain configuration
--------------------------------------------------
Device  ID Code        IR Length    Part Name
1      4ba00477          4        Cortex-A9
2      23727093          6        XC7Z020




JTAG chain configuration
--------------------------------------------------
Device  ID Code        IR Length    Part Name
1      4ba00477          4        Cortex-A9
2      23727093          6        XC7Z020


--------------------------------------------------
Enabling extended memory access checks for Zynq.
Writes to reserved memory are not permitted and reads return 0.
To disable this feature, run "debugconfig -memory_access_check disable".


--------------------------------------------------


CortexA9 Processor Configuration
-------------------------------------
Version.............................0x00000003
User ID.............................0x00000000
No of PC Breakpoints................6
No of Addr/Data Watchpoints.........4


Connected to "arm" target. id = 64
Starting GDB server for "arm" target (id = 64) at TCP port no 1234
System reset successfully


Note:: init_user command is Deprecated. Use ps7_post_config from ps7_init.tcl
Downloading Program -- zedb_host_if.elf
        section, .text: 0x00100000-0x0011a25f
        section, .init: 0x0011a260-0x0011a277
        section, .fini: 0x0011a278-0x0011a28f
        section, .rodata: 0x0011a290-0x0011ab67
        section, .data: 0x0011ab68-0x0011b7a3
        section, .eh_frame: 0x0011b7a4-0x0011b7a7
        section, .bss: 0x0011b7a8-0x001f67b3
        section, .mmu_tbl: 0x001f67b4-0x001fbfff
        section, .ARM.exidx: 0x001fc000-0x001fc007
        section, .init_array: 0x001fc008-0x001fc00f
        section, .fini_array: 0x001fc010-0x001fc013
        section, .heap: 0x001fc014-0x0020601f
        section, .stack: 0x00206020-0x0021ac1f
Download Progress..10.20.30.40.50.60.70.80..90.Done
Setting PC with Program Start Address 0x00100000
Processor started. Type "stop" to stop processor


RUNNING> Disconnected from Target 64


Disconnected from Target 352[/code]


Checking TeraTerm, it appears that the process does not get past the PHY auto negotiation:


[code]

-----Zedboard host interface TCP/IP server ------
Board IP: 192.168.1.10
Netmask : 255.255.255.0
Gateway : 192.168.1.1
Start PHY autonegotiation
Waiting for PHY to complete autonegotiation.
[/code]


The version of the original .bit file that I have on my PC is 3,951 KB (and all the modified versions I've made are also 3,951 KB), but the one you have attached is 2,118 KB.

Attached are the reference files try using these with no changes.
I have an idea about what may be causing this. I noticed that my frequencies are 2.5x the frequencies that are expected. I also remembered that the FCLK0 output from the Zynq processing block which drives the AXI interconnect and the AXI2SIP block is set at 50 MHz. FCLK2 was set to 125 MHz, but this block was not connected. Since 125 = 2.5 * 50, perhaps this is the issue. I will recompile the design with a 125 MHz FCLK0 and provide an update.


Edit: Changing the FCLK0 from 50 MHz to 125 MHz did not change anything. However, if I change the way the demo application computes the frequencies (i.e. in fmc30rf_freqcnt.cpp, I changed float testClkPeriod = 1.0f/125.0f to testClkPeriod = 1.0f/50.0f;), I get the exact results you have, the PHYs are 122.88 MHz and the CDCE62005 spare is 245.76 MHz. Surely this isn't a coincidence? Do you have any ideas?
Serial number is NCJ000053 and we are using a Zedboard. I have heavily modified the reference design, but I went back and tested the board using what I believe are the original .bit file, original .elf file, and the original reference application. Here is the full output:



C:\Program Files (x86)\4DSP\FMC Board Support Package\Refs\Software\FMC30RF - Co
py\Debug>Fmc30RFAPP 2 192.168.1.10 1000 2000 2000




Connected FPGA Device Type: UNIDENTIFIED DEVICE


Start of program
--------------------------------------
Constellation ID : 316
Number of Stars  : 5
Software Build  : 0x52289304
Firmware Build  : 0x00000000
Firmware Version : 0.1
--------------------------------------


Found ZEDBOARD hardware


---  Measuring on-board voltages  ---
5.0V DAC    : OK ( 4.96V)
3.3V CLK/VDD : OK ( 3.24V)
1.8V VDD1/2  : OK ( 1.81V)
4.0V RF      : OK ( 4.00V)
5.0V TRF37xx : OK ( 4.95V)
3.3V TRF37xx : OK ( 3.25V)

3.3V TCXO    : OK ( 3.26V)
VADJ        : OK ( 2.49V)
Temperature  : 36 C
--------------------------------------


Using onboard reference source...
Wait for PLL lock...
CDCE62005 PLL locked
Wait for PLL lock...
TRF3765 PLL locked
FMC30RF range 2 (1200MHz to 3000MHz)
Offset calibration busy
Wait for PLL lock...
TRF3720 PLL locked


Training status : Ready
--------------------------------------
IDELAY Ch: 12 | 11 | 11 | 10
Checking LO_RX and LO_TX Frequencies
High frequency range (1200 MHZ to 3000 MHZ) FMC30RF card detected
--------------------------------------




--- Measuring on-board frequencies ---
Stellar IP Clock : 125.00 MHz
ADC PHY Clock    : 307.21 MHz
DAC PHY Clock    : 307.21 MHz
CDCE62005 Spare  : 614.40 MHz
--------------------------------------


Retrieve 16384 samples from Receiver


End of program.




Press any key to continue . . .






Do you have a way of sending me an exact copy (.bit, .elf and demo .exe) of the files you're using that obtain the 122.88 MHz so I can check those on my card?
Hi BlakeM,


What is the serial number on your board? Are you using the .bit file provide by 4DSP and the reference application without any changes? What carrier board are you using?


This is what I would expect from the reference application:



--- Measuring on-board frequencies ---
Stellar IP Clock : 125.00 MHz
ADC PHY Clock    : 122.88 MHz
DAC PHY Clock    : 122.88 MHz
CDCE62005 Spare  : 245.76 MHz
--------------------------------------




That clock depicted in the SD11, FMC30RF Star just shows that there is clock generated by the FPGA which goes to the FMC to to the DAC (122.88 * 3 =  368.3).













Thanks for the info. I came across that section of the user manual about 30 minutes after I posted my question, so I understand the clock paths on the RF card itself (we have the range 2, 1200 to 3000 MHz card).


My other question, which I haven't figured out yet, is why the ADC/DAC clock rates reported by the reference application are 307.19 MHz (or ~10x the 30.72 reference)? I was expecting 245.76 MHz (OUT0 from the CDCE60025, which is sent to the FPGA)? I'm also not clear on what the 368.64 MHz clock is (depicted in SD111, FMC30RF Star.pdf)?
[size=1em]Hi,[/size]

[size=1em]Do you have the FMC30RF user manual? It shows a block diagram on how the clocking is done. It shows that what is used is:[/size]

[font=arial][size=1em]TRF3765[/size][/font]
[font=arial][size=1em](ACTIVE) 300M-4800MHz Low Noise Integer-N/Fractional-N PLL with Integrated VCO and up to 8 Outputs[/size][/font]

[font=arial][size=1em]CDCE62005[/size][/font]
[font=arial][size=1em](ACTIVE) 5/10 Outputs Clock Generator/Jitter Cleaner with Integrated Dual VCO[/size][/font]


[size=1em][font=arial]It shows that a 30.72MHz TXCO goes into a [/font][font=arial]CDCE62005 (clock generator), then from that clock generator you get a clock to [/font][font=arial]AFE7225 which is the ADC/DAC. That clock generator chip is programmable, the registers are memory mapped through the command interface. The reference software is an example on how that is used to set the clocking frequency.[/font][/size]


[font=arial][size=1em]Do you the FMC30R with [/size][/font]

[font=arial][size=1em]range 1  400MHz - 1200 MHz[/size][/font]

[font=arial][size=1em]or[/size][/font]

[font=arial][size=1em]range 2 (1200MHz to 3000MHz)[/size][/font]