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wh_in and wh_out wormhole format

Hi, I'm using 4DSP reference design and I cannot find any information about wh_in and wh_out internal format. In SD111 pdf file wh_in and wh_out are described as:



[u]wh_in[/u]
The 12 bits data for each DAC channel should be left or right justified (depending on register
setting) to 16 bits. Sample from channel A and B should be interleaved and de-multiplexed to
64 bits. The 64 bits data should be mapped to the Tx input wormhole. This is basically a
complex data wormhole. The description of the wormhole is given in the next table.


Output data bus is defined as a 64 bit port but no idea how it is internally organized. Could you provide more information on that?


[u]wh_out[/u]
The 12 bits data from each ADC channel is left or right justified (depending on register
setting) to 16 bits. Sample from channel A and B are interleaved and de-multiplexed to 64
bits. The 64 bits data is synchronised to the cmd_clk clock domain and mapped to the Rx
output wormhole. This is basically a complex data wormhole. The description of the
wormhole is given in the next table.


[font=Verdana]Output data bus is defined as a 64 bit port but no idea how it is internally organized. Could you provide more information on that?[/font]

[font=Verdana]Best regards[/font]

Dear Arnaud,


I appreciate your advice, and it seems that there is no other way to answer my simple questions. I would have to spend some time performing tests while 4DSP Support could answer them in a few minutes. I think 4DSP should take more care about customers satisfaction.


Best regards,


Sergio
Sergio,


The reference design is free of charge, you are free to use it or not. Some skilled customers implemented their product solely relying on the user manual and the chips datasheets.


Your comments about whether or not the forum should close forever or not is simply not right, 4DSP will ban you from the forum. Please focus on the firmware source code and less on writing long complaint posts, this is only an advice.


Best Regards,
Arnaud
Dear Arnaud,


First of all I would like to inform you that I'm not modifying anything of 4DSP firmware and as you wrote I'm just trying to understand it. I'm just using FMC30RF Star IP Core as it was delivered by 4DSP and I have to feed and receive data samples from these ports. In my opinion it is just a matter of having a complete definition of these signals. We bought this board which includes this reference design and at least I will expect to receive this kind of information. I'm not requesting you of course a line by line assistance (I'm very impressed about your conclusion) I'm only requesting you to clearly define [b]your [/b]interface. If you provide this FMC30RF Star IP Core I'm sure you have this information and I cannot understand why it is not provided.


For the other hand, your argumentation about how other customers were able to have a successful integration without this information for me it is not valid. If you think that your argumentation is valid obviously this forum makes no sense and 4DSP could close it forever.


Anyway, I'm sure you could be more clear than this:


[quote]I believe a word of 64 bit will look like that


A0 - B0 - A1 - B1 then
A2 - B2 - A3 - B3 then
A4 - B4 - A5 - B5 then
...[/quote]


For instance, I have several questions about this:
[list type=decimal]
[li]I'm assuming that A0 and B0 corresponds to LSB bits. Am I right?[/li]
[li]After mapping A15-B15 bit, 32 bits were used, what goes after? I mean, which data should I map after those 32 bits to reach 64 bit length?[/li]
[li]I am a bit concerned about your phrase 'I believe...' . Could you confirm that this is the actual definition?[/li]
[/list]


Best regards


Sergio
Dear Sergio,


I cannot be more clear than I was already sorry for that. The data wormholes are defined as 64 bit so it makes sense to have everything arranged as 64 bit. You have a reference design which works so please refer to it.


You can also simulate the design, this should help you out. Anyway you will need to understand the firmware in order to modify the firmware and 4DSP will not be able to assist you line by line unless an extended engineering support is purchased from us.


Many customers are using FMC30RF and some of them already completely integrated the product without this question so I assume it should be something you can answer also.


Best Regards,
Arnaud



Dear Arnaud,


Indeed, before posting in this forum I tried to have a look at the VHDL code but I didn't manage to find out this information clearly. I'm not so sure to understand the VHDL code since the transformation between the 64 bit representation to 32 is embedded in the Waveform Memory or the output FIFO (for wh_in.indata or wh_out.outdata respectively ) of the FMC30RF Stellar IP Core. Also I still don't understand why using a 64 bit representation since Channel A/B samples are 16 bit (indeed they are 12 bits but they are aligned left or right to 16 bits). Could you please provide me a clear definition about wh_in.indata or wh_out.outdata signal internal structure?


Best regards


Sergio
Dear Sergio,


Looking at the firmware source code can surely answer that. I am going to explain the way I understand it but you want to confirm that with the source code.


I believe a word of 64 bit will look like that


A0 - B0 - A1 - B1 then
A2 - B2 - A3 - B3 then
A4 - B4 - A5 - B5 then
...


Best Regards,
Arnaud

Hi Arnaud, thanks for your quick reply. I would try to explain my question better.


As you wrote:


wh_in is defined as:

in_data 64 bit (input, data)
in_stop 1 bit (output, stop)
in_dval 1 bit (input, data valid)


wh_out is defined as:


out_data 64 bit (output)
out_stop 1 bit (input)
out_dval 1 bit (output)


That is clear, I found this information in the SD111 pdf file (v1.0) where the FMC30RF Star is described. My question is about the internal organization of the wh_out.outdata and wh_in.indata signals[font=verdana, arial, helvetica, sans-serif][size=1].[/size][/font]


wh_out.outdata is defined as a 64 bit signal. I am assuming that DAC Channel A and Channel B bits (which at the end corresponds with I/Q signals) should be mapped into wh_out.outdata but I didn't manage to find any information about how it is internally organized. Which bit indexes corresponds to Channel A/B within wh_out.outdata? Why using a 64 bit signal to map Channel A/B signals(Channel A/B signals are defined as a 16 bits signals)?



Regarding wh_in.indata is more or less the same question, wh_in.indata is defined as a 64 bit signal. I am assuming that ADC Channel A and Channel B bits are mapped into wh_in.indata but I didn't manage to find any information about how it is internally organized. Which bit indexes corresponds to Channel A/B within wh_in.indata? Why using a 64 bit signal to map Channel A/B signals(Channel A/B signals are defined as a 16 bits signals)?


Best regards


Sergio
Dear Sir,


I am not sure about the questions, I assume you are looking for the low level details of the port. If so,


wh_in is defined as:


in_data 64 bit (input, data)
in_stop 1 bit (output, stop)
in_dval 1 bit (input, data valid)


wh_out is defined as:


out_data 64 bit (output)
out_stop 1 bit (input)
out_dval 1 bit (output)


You can check what wormholes are made from using the "Wormholes Editor" tab in the main GUI. Simulating/Chipscope the reference design might help understanding what the sequencing looks like.


Best Regards,
Arnaud
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