Hi 1. We have purchased "4 DSP FMC150 ADC/DAC" card. We need to configure ADC in CMOS parallel mode at sampling rate of 20MHz. How to configure it or how to control the sampling rate of ADC ? Could you send us sample code dealing with above requirement?
2. We have gone through CDCE72010 datasheet and found that it can also be used as global clock source(for our case 40MHz) for virtex 6 FPGA.How to make use of it? 3. How to configure ADC in CMOS parallel mode in offset binary format?
about 5 years ago
1&2. Having found no good way to slave the ADC to the board clock, we run the ADC at its native 245.76Ms/s and drive most of our signal path from that clock, w/ appropriate downcounted enables. Do you require precisely 20MHz, or would 245.76/8 or 245.76/16 be close enough? By using more elaborate multirate digital filters than the simple half-banders we are using, you should be able to get fairly close to 20MHz.
3. The easiest way to convert between two's complement and offset binary is simply to flip the MSB in your digital logic.