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Interfacing the FMC150 and ML605

[color=#1F497D]I am trying to implement an interface wrapper between the FMC150 and ML605 so I can interface my designs with the FMC150. I have looked through the the RTL reference design from Avnet and the FMC150 user manual from the website. However, I am having some difficulty understanding some of the SPI control signals. Are there any resources/designs available which can give a description for these signals and how they can be used? [/color]

Dear Sir,

We do not have more documentation than the user manual. However we have a reference design Avnet customers can purchase separately from [email][/email]. It is an ethernet reference design able to offload ADC snapshot to the host. It also includes a complete simulation environment for modelsim as well as StellarIP itself.

With my best regards,

Hello lhanyong -- as a fellow 4DSP customer, I feel your pain. I, too, am struggling with the clocking of the interface between the FMC150 and the ML605. I simply want my baseband modulator to drive the DAC and my baseband demodulator to receive data from the ADC, which is about as simple an FMC150 application as I can envision. I am doing this by hacking the HDL Coder- generated VHDL to insert the DAC and ADC into the loop, to get things up and running in a simple loopback test.
Dear Avnet Users,

If I am not wrong avnet made FMC150 schematics available to public. Engineering is unfortunately not about compiling a reference design which perfectly fits your needs and claim job done.

Having FMC150 schematics and datasheet of the various components part of FMC150 should be enough to do anything, the sky is the limit :)

With my best regards,

Perhaps I am being "thick," but I am having trouble seeing where to modify the A/D and D/A control logic to change the clock rate and/or to slave the FMC150 to the clock in my FPGA. When I have written control code or designed ICs, I have started w/ a table of control and status register (CSR) values which the control code automatically loads. All my customer had to do was to edit the CSR table appropriately to put everything into the proper mode.

For example:
1) Specifically how would I tell the FMC board to run at 122MS/s instead of 61?
2) Specifically how would I tell the FMC to run on a clock which I generate on the ML605?


1) I can generate a single-ended 2.5V clock of approx. 62.5 or 125MHz at ML605 SMC jack USER GPIO P.
2) I can drop this to 1.3V using a 50ohm inline attenuator and route it into the FMC150 clock input port.
3) I can set the external_clock control bit on the FMC150 board.

Do I need to do anything else to slave the ADC/DAC clocks to those of the FPGA, instead of the default other way around?

Has anyone successfully done this? Are there any other gotchas of which I should be aware?
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