months ago I started a topic tittled "FMC116 Initialization Problem".
What I needed was to change the sampling rate from 125Mhz to approx 10Mhz, and I used registers to change ADC sampling clock speed. That solution was not working as can be read in referenced topic, so I left ADC sampling clock to 125Mhz, and put a CIC filter with downsampling after ADC output. It works correctly.
But now I have to set sampling frequency even lower, and maximum downsample factor value of CIC filter is not enough for me.
First solution that comes to my mind is to write a simple vhdl module that only accepts one of each N samples comming from ADC. This way, if N is for example 5, real ADC sampling frequency going to CIC filter would be 25Mhz.
So the real questions are :
Is it equivalent to use 125Mhz clock and described vhdl filter with N=5 than setting ADC sampling clock to 25Mhz? Does FMC116 any kind of antialiasing filtering with read samples?
Thanks a lot