Recently we bought a FMC230 board, but we are reporting some problems in the DAC0.
We are using the VHDL reference design provided by 4DSP for ML605 board, including also a VHDL code created by us to generate a NRZ signal at 1.25 Gb/s (2 samples per symbol at ~2.5 Gsa/s) for both DAC from a PRBS. We send exactly the same signal for both DAC.
The DAC1 works without problems, however we are observing problems in the DAC0. It only works for smaller bit sequences (<128 bits). With the sine wave by default it works. If the bit sequence is large, the synchronization of the DAC0 is lost. We think that the problem is the phase sync, sometimes the phase seems to change (see the picture that I attached with the NRZ eye diagram in DAC0 and DAC1 – the signal in DAC1 must be the same in DAC0).
We also tested several ODelay in C code and even in the VHDL, but without success. Do you can help us?
Ricardo M. Ferreira