I am trying to modify the output of Stellar IP design 243_vc707_fmc110 which comes with the BSP, to use only ADC0 of FMC110. However when I try to synthetize the generate project, ISE is throwing errors in MAP process.
I fixed it by the IOSTANDARD from LVDS_25 to LVDS in both VHDL and UCF files, however I am not sure if changing it will result in malfunction or even damage one of the boards.
Does anybody know if I can do it?
I checked the datasheets of the Virtex 7 FPGA and ADS5400, and it seems to be compatible, but I am not sure.
Thank you in advance.