We would like to import the FMC150 ip cores geneated by ml605_fmc150 reference design to the Xilinx Platform Studio, and collaborate with our WARP board. However, we encounter a lot of errors like that:
NgdBuild:604 - logical block
'fmc150_0/fmc150_0/sip_fmc150_0/fmc150_if_inst/fmc150_ctrl_inst/adc_cmd_pls[8 ].pulse2pulse_inst' with type 'pulse2pulse' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'pulse2pulse' is not supported in target 'virtex6'.
We either add pulse2pulse.vhd into the ip core folder or not, this type of error is still there. Could we get some advices on this error?