The VP881 and VP889 hardware has been updated to include hardware write protection of the Zynq non-volatile memory through NVMRO:
Figure 1: Original design (r1.0 and r1.1 PCB)
Figure 2: New design (r2.0 PCB)
This hardware change requires modifying the Zynq first stage boot loader (FSBL) in order for the Zynq to correctly load from non-volatile board memory when NVMRO is asserted.
The change is backwards compatible with r1.0 and r1.1 PCBs and is present in VP88x_2017.3_r5 or later versions of the VP88x Petalinux download. Alternatively, the modifications may be made to the FSBL boot code in order for the board to function correctly. These changes allow the non-volatile QSPI memory connected to the Zynq to correctly use the dual purpose write-protect and data pin as a write-protect pin.
- Browse to the xparameters.h file located in components/plnx_workspace/fsbl/fsbl_bsp/psu_cortexa53_0/include
- Change line 940 from:
#define XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH 2
#define XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH 1
- Follow the standard Petalinux build procedure in UM080 (VP880/VP881/VP889 Software BSP Manual) in order to complete the build process. Be sure to run the following command before rebuilding:
petalinux-build -c fsbl -x cleanall