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Systematic Design Methodology with FMC ADC

Dear Arnaud

I want to integrate my own HDL codes with FMC112 firmware, to achieve my desired functionality. Is there any doc to streamline the integration methodology? Stellar IP is a good point to start, however I cannot find a good document on integration of my own "Non-AXI" codes in Stellar IP environment. Could advise me on that?

In addition, the interaction with Ethernet(from PC side), remained unclear for me, since I got to write a program in PC, in order to send commands to the FMC firmware and associated 4DSP IP cores, resembling "FMC Analyser" performance in sending command and retrieving data, with some other functionalities. could you please hint me to a good documentation?

Dear Karen,

For the first one, not sure what you are searching really. Are you unable to convert something to be using StellarIP simple data interface (64 bit data bit, one data valid strobe and one data stop)? If that is the question, no sorry we do not have more documentation but still we documented how to wrap an AXI streaming interface towards StellarIP. A very simple example you can look at is the fifo 64kB we have in the training material, we describe how to create a 128kB FIFO from the 64kB FIFO which is not Axi. You could also look at the stars delivered as source code, data routers, etc..

For the second one, check the sipif.cpp module or its doxygen (the doxygen is part of the software source code). sipif_readdata() are sipif_writedata() are both exercising the data bus and sipif_readsipreg() and sipif_writesipreg() are exercising the command bus (the host interface and/or mac engine have one command wormhole pair and one data wormhole pair).

The FMC Analzyer is built using same source a FMC112App in fact. There is just a wrapper around the reference application code, nothing fancy the reference software code is reused as is in the FMC Analyzer.

I hope that helps,

Thanks for your reply, Arnaud.

About "create a 128kB FIFO from the 64kB FIFO which is not Axi", where can I find the documentation?
Hello Karen,

Chapter 6 in the 4FM Getting Started Guide (StellarIP Star Creation). I know this is copy paste but still all the steps are there. This is as simple it can get.

Best Regards,

Dear Karen,

I am following up with you. Any progress on your side?

Best Regards,

Thank you for your responsibility but look, There is a major problem.

in the example of changing fifo from 64 to 128, we are not really engaged with changing the interfaces required for the XilinxIPcore to be compliant with stellarIP environment, specifically, we dont really change the following files:
unless some renaming. custom designs does not neccessarily have the same IO, timing, ...

So, In order to realize what is really happening inside the system, designer need to insert chipscope into the design to watch the way signals are exercised in the system(simuilation does not provide practical help)

The chipscope is really cumbersome and frustrating. Do you have any example, create a stellarIP core from NEW hdl codes, creating interfaces and inserting into the StellarIP environment? I believe such a high tech boards, deserve much better documentation.

Dear Karen,

I appreciate the fact you are disappointed about our reference and documentation. The thing I don't understand is whether or not you are blocked, cannot moved forward or is it some feedback you are providing us.

If you are blocked on something, please let me know what this is and then I will provide you with answers to your questions. Otherwise, please let me know so I can lock this topic.

Best Regards.


1. Should I continue with your simulation scripts and inserting Chipscope into the design to completely understand the interface you are using in the stellarIP, or there is another way to do that?

A possible solution might be creating a completely new "star", creating the StellarIP interface codes from scratch and importing into design ... , Do you have such an example design?

2. My problem is that, I created a wrapper for my HDL codes, based on the fifo example, but the output I'm getting on PC side is all zero. I cannot verify whether my interface (from HDL codes to StellarIP) is the problem or not, What is the solution for that?
Dear Karen,

Creating a complete star from scratch is covered by XFFT training material. A star is created from scratch and an AXI interface core is wrapped by the star.

Please let me know if you have any other questions before I close this topic.

Best Regards,

Dear Karen,

I see you have edited your posted and added a second question. As far as this question is concerned, have you simulated your design? I don't know about you but our firmware engineers are always simulating their designs. moving to implementation as soon that is working but they are not coding and implementing their design without simulation.

The fact you get data on the PC side means that the transfer between the host interface and the host worked fine, for the rest, simulation/chipscope will tell more. You will need these tool during your development, this is certain.


Dear Arnaud,

Let me dig deeper into the source codes, and in case I still got problems, I will ask for your advice.

thanks again and you may close the topic.
This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.