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FMC 164/168

I was told that the ADC chips on these boards could be configured such that they capture data out of phase with respect to each other - is that true and if so how to you configure them?


This is not the case, the ADCs are all sampling on the same clock. The ADC chips don't have a feature to delay/phase shift the clock internally.
The ADC chips have settings for delaying the QDR/DDR output clocks but this is the digital domain and not the sampling clock.

Best regards,
Ingmar van Klink
Dear Sir,

With you permission I will lock this topic, the issue being asserted I believe.

Best Regards,
This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.