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How to control the FMC116 board and set important parameters?

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I have an FMC116 ADC Board on a VC707 Evaluation Kit. There are several problems to which I need answers.

1.      What tools do I need to program and control the FMC116 board? For example if I want to set the sampling rate, reference voltage, what tools should I use to set these parameters? Is it Stellar IP that I should use?

2.      After I set those important parameters with some tools, how should I transmit the data from the board to PC? Do I need to develop an application? What tools do I need to realize the communication between FMC116 (which is plugged on VC707) and PC?

3.      In chapter 8 of the “4FM_Get_Started_Guide”, I went through the contents in 8.1 and managed to retrieve some reasonable data. It seems that we only download a firmware to FPGA but does not download anything to the CPLD on FMC116. I want to know how the parameters (like sampling rate, reference voltage and clock) are set in this case.

4.      Besides I want to know how to make a firmware and a Stellar Definition File for a specific design.

It will be very nice of you if you can give me answers to those problems. What I am trying to accomplish now is to use FMC116 to sample and convert analog inputs into digital form, transmit the data to a PC and display it on the screen in real time. This sounds a very straightforward design, doesn’t it? Could you give some suggestions and guides?  Like what the design flow looks like and what tools I will need to accomplish the design?
Thank you very much


Dear Xun,

The first thing I want to suggest is an online training session provided by 4DSP. It seems like it might be useful for you. You can arrange that with

1. StellarIP creates a Xilinx ISE project which can be loaded in Xilinx ISE in order to compile a firmware for VC707. The control of the hardware as initialization is done by a software running on a host computer during runtime, configuring data formats, sampling frequency, etc.. The software can either use Ethernet or PCI (PCI is a paid option).

2. The reference software application does save buffers to hard disk and the samples are retrieved by Ethernet or PCI (PCI is a paid option).

3. All the parameters are set during runtime by the software application over Ethernet or PCI (PCI is a paid option). The CPLD is a blackbox delivered pre-programmed. The software application is based on Visual Studio 2012.

4. For this you will need to do as other customers, understand StellarIP based on the training materials (none for VC707 available but some others for ML605, which is the same thing besides the target hardware) and the FMC110 reference design or simply forget about StellarIP; As soon you get the Xilinx ISE project out of StellarIP you can simply edit/modify the firmware in Xilinx ISE this is a common firmware design flow, technical support for these tools is provided by Xilinx and not 4DSP.

"[font=times new roman][size=14px]What I am trying to accomplish now is to use FMC116 to sample and convert analog inputs into digital form, transmit the data to a PC and display it on the screen in real time."[/size][/font]
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Taking snapshot of data and display it on the screen 5 times per second must be achievable. Not sure what your real time definition is but if you mean streaming the 16 channel at 125Msps then you need:

16 channels * 2 bytes per samples * 125 million times per second is -> ~3.9GBytes per second. This is not physically possible on Ethernet or PCI.
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[size=4] [font=calibri]Dear,[/font]
[font=calibri]Thank you very much for your reply. I really appreciate your help. Here I have some more questions. I hope you could take a look and give me some suggestions.[/font]
[font=calibri]1.[/font]      [font=calibri]It looks like it is not possible to transmit data between FMC116 and PC in real time. What about the maximum data rate between FMC116 and VC707? Now I want to acquire data and store it in the DDR3 memory on VC707 first and transmit it to the PC later. I really want to know the maximum data rate between FMC116 and VC707 with a sampling rate of 125MSPS.[/font]
[font=calibri]2.[/font]      [font=calibri]When learning to use the stellar IP Constellation Editor, I noticed that every star always has a “cmdclk_in” signal, a “cmd_in” signal, “cmdclck_out” signal and “cmd_out” signal. Some stars have “clk” signals. I just want to know why a single star could have two clock signals. Is it because we want to separate the control flow and data flow apart? In my understanding, “cmd_in” is a signal which controls a star and “cmd_out” is the feedback from that star for the control signal. Is this understanding right?[/font]
[font=calibri]3.[/font]      [font=calibri]I find it a little difficult to integrate the stellar IP firmware with my previous ISE project. If I just want to set important parameters (sampling rate, reference voltage, internal or external clock) for FMC116 without creating any firmware, what is the right thing to do? Is it possible to develop a software application to set those parameters without creating firmware using stellar IP?[/font]
[font=calibri]I am a beginner and some of those questions may not make much sense for you who may be already expert in this area. But I will really appreciate it if you could offer some suggestions.[/font]
[font=calibri]Thank you very much[/font]
Dear Xun,

1. The maximum sampling rate is 125'000'000 samples per seconds * 16 channels * 2 bytes per samples is equal to 3814 MB per second. This is what the A/D chips can output. This is too much data for any streaming application. I am not sure if the FMC116 star has enough bandwidth. Typically on the data wormhole we have a clock of 125MHz and the bus is 64 bit wide. This means one data bus can sustain 125'000'000 * 8 bytes, This is 953MB per second. You will need to redesign the buffering, most likely modify the star to use several wormholes, etc.. Also don't forget the bandwidth writing to DDR3; It might be that you don't have enough bandwidth on the DDR3.

2. Correct, some stars have a different clock, one clock is for the command architecture, generally 125MHz but typically sometimes you want a higher clock frequency for the processing. Also correct cmd_out is the way a star can output values on the command bus.

3. You could indeed use the default reference design and simply code your software. The current reference design is a bit constrained as typically you will not get more than 10-15MB/s using ethapi. This interface is not suited for streaming large amount of data but simply offload some snapshots.

Another thing, in the reference design, the 16 channels are not synchronous because the firmware architecture. You will see a phase difference between the channels. Having 16 channels sampling synchronous is something to be asserted by the integrator.

I hope that help,
[size=4]Dear Arnaud,[/size]

[size=4]Thank you for your response.[/size]

[size=4]Today I tried generating a Xilinx ISE project out of Stellar IP with the firmware provided by 4DSP. I found the firmware in this directory: “C:\Program Files (x86)\4dsp\Common\Firmware\Extracted\248_vc707_fmc116” and copied this folder to another directory:” C:\Users\xwu12\248_vc707_fmc116”[/size]

[size=4]First I opened the 4FM GUI Control Application and set the SDF File Path to be:” C:\Users\xwu12\248_vc707_fmc116\implement\vc707_fmc116.sdf”. And then the Library File Path was set automatically to be:” C:\Users\xwu12\248_vc707_fmc116\star_lib\library.xml”. I clicked the “generate” to generate an ISE project.[/size]

[size=4]Then I opened that project and started synthesizing and implementing the design. The synthesizing process went well, but I couldn’t implement the design or generate a bit stream file because of the following error:[/size]

[size=4] NgdBuild:604 - logical block[/size]

[size=4]  'sip_fmc116_0/fmc116_if_inst/ltc2175_phy_inst' with type 'ltc2175_phy' could[/size]

[size=4]  not be resolved. A pin name misspelling can cause this, a missing edif or ngc[/size]

[size=4]  file, case mismatch between the block name and the edif or ngc file name, or[/size]

[size=4]  the misspelling of a type name. Symbol 'ltc2175_phy' is not supported in[/size]

[size=4]  target 'virtex7'.[/size]

[size=4]There are 40 errors, all of them are of the same type as above. I checked and found that many files are missing, like “ltc2175_phy_inst”, ”ltc2175_16to16_inst”, ”ltc2175_cbfifo_16to64_inst” and so on.[/size]

[size=4]I am very confused about this. Am I missing some steps? How do you get the bit stream file in the directory:” C:\Program Files (x86)\4dsp\Common\Firmware\Recovery\248_vc707_fmc116”? I mean the bit stream file we use to run the reference design for VC707 and FMC116. Isn’t it retrieved by using the firmware to generate an ISE project and then generate a bit stream file?[/size]

[size=4]I appreciate your time reading this message.[/size]

[size=4]Thank you very much.[/size]



It sounds like there are some design files missing. Could you regenerate the ise project using the StellarIP tool and check if the files listed in the "\248_vc707_fmc116\star_lib\sip_fmc116\sip_files_v7.lst" match to "\248_vc707_fmc116\output\vc707_fmc116\Src\sip_fmc116"? If not, could you delete "..\vhdl\pulse2pulse.vhd" in the "sip_files_v7.lst" and regenerate the StellarIP tool. If you still have missing files, please let me know.

[size=4]Dear Kyu,[/size]

[size=4]1.      I did not find a file with the name “sip_files_v7.list”, but I found a file with the name “sip_fmc116_v7.list”. Is this the file you meant?[/size]

[size=4]2.      The files listed in “sip_fmc116_v7.list” did not match to "\248_vc707_fmc116\output\vc707_fmc116\Src\sip_fmc116. So I deleted “..\vhdl\pulse2pulse.vhd” and regenerated an ISE project out of stellar IP.[/size]

[size=4]3.      It worked! I generated a bit file (although with many warnings together), downloaded it into the FPGA and then called the fmc116 application and finally managed to retrieve some reasonable data.[/size]

[size=4]Thank you very much for your suggestion! But actually I am still not very clear why this problem can be solved this way. Could you give an explanation for this?[/size]

[size=4]Besides, I want to know how a firmware is made from beginning to the end. Does it start from making a schematic with the Stellar IP Constellation Editor? After completing the schematic, we export an sdf file and then generate an ISE project. Is this how it is done? [/size]

[size=4]One final thing I want to know is how to develop the software to control the kit. I want to modify the design (or create a design on my own). The corresponding software also has to be changed, right? Could you recommend some references about it?[/size]

[font=calibri][size=5]And another thing is that, in the reference design for FMC116 and VC707, the 16 channels are not synchronous. Now I really want to modify this design so that the 16 channels can sample and acquire data simultaneously. I know this modification may be complicated. But could you give me some suggestions as how I should start? What corresponding modification do I need to make to the software for this design?[/size][/font]
Dear Xun,
Please contact your sales point or contact [email][/email].
We can offer you a training of 1, 2 or 3 hours where we will be able to help you out in details. You could also purchase a engineering support contract where you will get detailed answers to your questions.
You can also follow the steps in the 4FM Getting Started Guide, they are covering creation of a firmware or stars. You can refer to the ML605 material which is similar.
Best Regards,
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Hello dear everyone,

I am now thinking about controlling the FMC116 using purely hardware. I am trying to build an initialization circuit for it. And there are some questions I want to solve first.

1.      What is the voltage range of the ADC on FMC116? Is it decided by REFH (Pin 6, 7) and REFL (Pin 8, 9) of the LTC2175-14 ADCs on the board? If so, what voltages are connected to those pins on FMC116 board? Is it possible to use external reference voltages?

2.      It looks like the frequency of the signal connected to ENC+ (Pin 17) and ENC- (Pin 18) of [/font][/size][/font][font=calibri][size=1.35em][font=times new roman][/size][size=3]LTC2175-14[/size][size=1.35em] decides the sampling rate, is this right? Are those two pins connected to clock signals coming from AD9517? If so, how are they connected? How can I set this sampling frequency purely through the SPI communication bus (without software)?  Could you offer the corresponding timing diagrams and register map for this?

3.      If I want to use external clock signal, I should first set “CLKSRC” of “CPLD_REG0” to be 00 and connect the [u]clk in[/u] on FMC116 to an external clock signal. What is next step I should do? Are there any other registers that I need to set?

4.      How many clock cycles should be left between two sequential SPI commands transmitted to CPLD?
[font=calibri][size=1.35em][font=times new roman]5.      What is the largest possible frequency of the SCLK (CTRL(0)) signal that acts as the command clock?[/font][/size][/font]

[font=times new roman]6.        [size=3]It seems that [/size][/font]the four [font=calibri][size=1.35em][font=times new roman]LTC2175-14 ADCs have four different clock signals. Is it possible to let them share one clock signal or make those four clock signals identical?[/font][/size][/font]

7.      I am feeling a little confused about the "clock" signal and "trigger" signal on FMC116. Could you explain to me the differences between them?
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Many questions are refering to the data sheet. I think the manufacturer can give better answers.

1. Our user manual says input voltage range is 2Vpp. We are following the datasheet. You may need to contact the manufacturer to have a bette answer.
2. Those signals are connected to ENC pins. To set the sampling frequency, I think this depends on how you implement it. We configure it with using the software because it's easy for customers to modify it. For the register maps, you can see in the datasheet. For our constellation register map, you can find it "firmware folder/output/xxx_xxx/Src/sip_cid/cid_package.vhd"
3. In our reference design, what you need to do is to provide the external clock and trigger and run the software application in the external clock mode.
4. Can you explain me more about this question?
5. You can also get it from the datasheet. The datasheet says the min clock period is 40ns for Write Mode and 250ns for Readback mode.
6. Yes. I think all 4 clock have the same frequencies in the reference design.
7. Trigger is a signal that tells the ADC to capture the data.

[font=times new roman][size=4]Hi Dear Kyu,[/size][/font]

[font=times new roman][size=4]Sorry for not having expressing the question well.[/size][/font]

[font=times new roman][size=4]1. Explanation to question 4: First I’d like you to look at Figure 11 in the FMC116_FMC112_user_mannual. There are three ports: SCLK, N_CS, SDIO which are connected to CPLD and we can program the device through these three ports, which are also connected to CTRL(0), CTRL(1) and CTRL(2) on the FMC connector.  Then I’d like you to look at Figure 12, which shows how to write some data into a register. You can see that N_CS is “0” for 24 cycles of SCLK. I just want to say that, N_CS is “0” for only 24 cycles in this case, right? It cannot be “0” for 48 cycles to write TWO registers, can it? We can only write one register a time, can’t we? If so, there must be some SCLK cycles between two sequential writing operations during which N_CS is “1”, right? I just want to know how many cycles there has to be between every two operations.[/size][/font]

[font=times new roman][size=4]2. I am still not clear about the trigger signal and clock signal. According to your answer, Trigger tells the ADC to capture the data. Then it is the trigger signal which decides the sampling frequency rather than the clock signal, isn't it? Then what is clock signal used for? Are there any constraints or relations between the frequency of trigger signal and that of clock signal?[/size][/font]

[font=times new roman][size=4]Xun[/size][/font]


1. You can only write one registers at the same time. SCLK is needed only when CS is enabled. So, I will say there should be no SCLK cycle is needed as long as ADC device detects the start and stop signals from CS. You can set N_CS to 0 and leaves it. It will be connected to one of CS only when the software communicates. Otherwise, it will be 1. If you see how it communicates in the software. It will be more clear.

2. When arm is asserted, ADC becomes ready to capture data and trigger tells ADC to start grasp the data and store it to the fifo. The ADC will capture the data at the sampling frequency. I think if you see a vhdl code "\4dsp\Common\Firmware\Extracted\xxx_xxx_fmc116\star_lib\sip_fmc116\fmc116_ctrl.vhdl", you can understand it much better.

[font=calibri]I have some new questions regarding FMC116. It is about applying high sampling frequency.[/font]
[font=calibri]1.[/font]      [font=calibri]The clock signal I used was a clock signal generated by the VC707 board. I connected this signal to the “Clock In” of FMC116. Then I set some registers in AD9517 (mainly 0x1e1, 0x192, 0x198, 0x232) so that this clock signal could be routed to the clock input of the four LTC2175s on the board. I tried retrieving and plotting data and it worked. But as I increased the frequency of this clock signal, the board became unable to work well. Before the frequency reached 18MHz, the data plot was very clean and clear. But as the frequency became larger, more and more glitches appeared in the data plot. When the frequency was 20MHz, the data plot was just like noise. But the maximum sampling frequency could be as high as 125MHz, couldn’t it? What may be the reason?[/font]
[font=calibri]2.[/font]      [font=calibri]One reason for the above problem I think may be because high frequency clock signals could not be transmitted through the cables onto FMC116 very well, so I tried using a 10MHz clock signal from VC707 as a reference signal and using the internal VCO and PLL on AD9517 of FMC116 to generate an on-chip high frequency clock signal. However the configuration seemed pretty complicated.  Could you tell me which registers I need to set to realize this configuration which can generate high frequency clock signals with a low frequency reference clock from VC707?[/font]
[font=calibri]For the AD9517 on FMC116, there are two reference input pins (REF1, REF2). Could anyone tell me how the external reference or internal reference is connected to those pins? Is it connected to REF1 or REF2? Or is it connected to both REF1 and REF2 as a differential reference pair?[/font]