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Hi again!
This is a simple question that I hope you can solve (as usual ;) )

I need to know what the sample order is in the 64bits word that comes from fmc116 in the whormhole to the buffers for the bursts.

Is it Sample3|Sample2|Sample1|Sample0 being bits 63 downto 48 for Sample 3, 47 downto 32 for Sample 2, 31 downto 16 for Sample1, and 15 downto0 for Sample0,

Or is it Sample0|Sample1|Sample2|Sample3 ?

Thanks a lot!!

Víctor Martín, IEEC

Dear Victor,


We have never received notifications about this post, have you figured out this problem already?


Thanks,
Arnaud

Hi Arnaud,
no, I haven't find it out. I assume that the order is the logical one. I suppose that I could test it using a known input, but I haven't tryied.For my current tests it is not the most important issue I have to solve ;)

I'm using a customized version of your reference software. In fmc116_ltc2175_fifo.vhd, I see that the output of the entity, if_data, is built using the output of the 16X64 FIFO, but changing the order:

if_data <= dout (15 downto 0) & dout (31 downto 16) & dout(47 downto 32) & dout(63 downto 48);

I don't know if it's because the FIFO reverses the order, or because the expected output must be ordered this way.

So it would be great if you could confirm which is the correct order.

Thanks once more!

Víctor

Victor,


It would be:


Sample3|Sample2|Sample1|Sample0


Please see http://www.xilinx.com/support/documentation/ip_documentation/fifo_generator/v9_3/pg057-fifo-generator.pdf


page 114.


Thanks,
George

Hi George,
thanks for your response.

Just to add some explanation in case someone is interested, reading  the core generator document you refer to, tells the following:

[i]For non-symmetric aspect ratios where the write width is smaller than the read width (1:8, 1:4,1:2), the most significant bits are read first.[/i]

It's related to the FIFO output. So the output from the buffer would be S0|S1|S2|S3 being MSB S0..
But the line of code that I commented on my previous post :

[i]if_data <= dout (15 downto 0) & dout (31 downto 16) & dout(47 downto 32) & dout(63 downto 48);[/i]

Reorders the samples in a "logical" order, being MSB S3, and LSB S0 in the output of the component that holds the FIFO.

So samples from this output can be read in a logical order from LSB to MSB as you said, S3|S2|S1|S0

Thanks a lot!

Víctor Martín, IEEC

Hi Victor


thank you for your response. I will proceed and lock the topic


Best regards,
Erik

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.