No output from channel1,2,3,4 or from channel9, 10, 11,12
started a topic
about 6 years ago
[font=times new roman] [size=12pt][font=calibri]Hello everyone,[/font][/size] [size=12pt][font=calibri]Sorry to bother you again. Thank you for all the help and instructions you provided before. Here I have one more problem again. It seems that I cannot observe and output signal from channel1~4 and channel9~12. [/font][/size] [size=12pt][font=calibri]First I plugged FMC116 to my VC707. Then I used the Differential Signaling Input Buffer (IBUFDS) to convert the LVDS signals from FMC116 to single-ended signals. After that, I routed those single-ended signals to the SMA connector on the VC707, connect them to the oscilloscope, and observe them.[/font][/size] [size=12pt][font=calibri]I could always see outputs from channel5~8 and channel13~16. But when it came to channel1~4 and channel9~12, I could not observe any signal at all, no DCO signal, no OUTPUT_A, nor OUTPUT_B. At first I thought the ADCs responsible for those channels might have been broken. But when I tested those channels with the reference design you provided, they worked pretty well.[/font][/size] [size=12pt][font=calibri]Could anyone give me a hint? What may be the reason?[/font][/size] [size=12pt][font=calibri]Thank you very much![/font][/size] [size=12pt][font=calibri]Xun[/font][/size] [/font]
[font=calibri]Hello Kyu,[/font] [font=calibri]The problem is solved. There are four registers (0F0, 0F1, 0F4, 0F5) on AD9517 which control the output clock signals that drive the four ADCs. The default configuration upon power on is that two clock signals working normally while the rest two partial powered down. As long as the values in those four registers are all set to be 0x08, all the ADCs will work normally.[/font] [font=calibri]Thank you for the suggestions you provided, too.[/font] [font=calibri]Xun[/font]
about 6 years ago
With the information you provided, it's very dificult to find the issue. Since the reference design works fine, I assume that your design or setting are not correctly implemented. At this stage, I recommend that you should 1. Compare the vhdl codes for ch1~4 and ch5~8 and see any difference. Some signals to ch5~8 and 13~16 may be rounted incorrectly. 2. Compare your design to the reference design. 2. Check the pin locations of ucf file.