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FM126 porting from ML605 to VC707

I am trying to port a design that we developed using your sample design on a ML605. I am having trouble related to the BUFR instance on Virtex 7. It has different restrictions on using BUFR in multiple clock regions. Now you must instantiate a BUFMR and multiple BUFRs. The problem is the VHDL sample placement isn't controlling the resource placement and uses 2 or more clock regions.  I need to get the reference design for the VC707 for Vivado, how do I proceed?  Or how do I guide the tool to force clock region restrictions on units?

Dear Sir,

We do not support Vivado yet there is many Xililinx literature covering how to migrate an ISE project towards Vivado, you are probably able to find your way through.

About clock region per unit, I believe Xilinx FAE should become handy on this one. Indeed there is big difference between V6 and V7, and you will see V8 is going to be great fun also..

The only firmware we have for VC707-FMC126 is part of the default BSP. We also have the calibration (for 1 and 2 channels mode) package.

Best Regards,

How do I get the updated BSP. The VC707 did not exist when we implemented the ML605, so the BSP we have doesn't include VC707 related. I just need to see how you handled the clock region in your design. Our FMC126 calibration is very heavily based on you ML605 sample design.
Dear Sir,

You can download the latest BSP from You will need your FMC serial number for that. I have also placed the firmware source on a private area (,2415.0.html)

I hope that helps,

Thanks for the files this helps.

I see that for FMC HPC2 on the VC707 you are calling out pins for A/D input channel D, but I thought those are no connects on a VC707.  Are they connected or not? I was targeting this board because I thought they were fully connected until I got deep into the documentation (which is full of typos on this interface). At which point I had to decide to move forward with a 7 channel (Two FMC 126 design on VC707) instead of all 8. This is disappointing managment.

So again are all 4 A/D channels connected on VC707 FMC HPC2???

That would be great.

Thanks Brad

Hello Brad,

VC707 HPC2 does not provide HB signals. Thus, ADC D is not possible. I don't know why there is another UCF file in the design file. If you see VC707 user guide, you can still see that there are FMC2_HPC_HBxx signals in the FMC connection table. I guess the designer initially referred the user guide. I will remove the ucf file for HPC2.


Thanks for the reply.

My question is will I be able to use FMC2 HPC2 as a 3 channel input for proof of concept. I do understand that I will have to make it so the calibration will succeed without the fourth channel. In other words will the A/D work on the other 3 channels without the 4th hooked up?



You can use 3 single ADC channels on FMC2 HPC. The calibration will work as well. I'm not sure if you purchased 4DSP calibration package. Our calibration package uses connector A for one channel mode and A-C connectors for 2 channel mode. You do not need 4th channel hooked up while calibration is performed. If you see the ADC device datasheet, you can find more details.

This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.