4DSP Products Technical support

I looked at the Post-Place & Route Static Timing report generated by ISE, and there are many paths under "Unconstrained path analysis - Hold paths" that are listed as failing.  It's not clear to me if these failing paths could cause problems, but it is concerning.  Shouldn't these paths be constrained?

Dear Sir,
Our designers place the required constraints generally. No action required I assume, first run the design and see if that works.
You can provide me with a list of unconstrained nets, we can look at it quickly but I am not too concerned about that.
Best Regards,
Arnaud

Here's the section of the timing report that lists the hold errors.

Hi


the report shows these are all cross clock domain paths. These are taken care of by design and do not require constraints.


Best regards,
Erik

That's good to know.  I think some timing ignores for these specific paths would be useful for indicating the intent that these paths are taken care of by design and getting rid of the hold errors in the timing report.